Electronic combination lock circuit
At power ‘on,’ capacitor C2 connected to pin 15 of IC1 charges to high level through 820-kilo-ohm resistor, holding the counter in the reset state. In this condition, output O0 (pin 2) of counter IC1 is high, while all other outputs are low.
When switch S2 is pressed, transistor T1 conducts and capacitor C2 discharges via diode D1 and resistor R2, releasing the counter’s reset input. When S2 is released, T1 cuts off and its collector is pulled high, generating a rising edge on the counter’s input clock pin 14. Capacitor C1 and resistor R3 in the base circuit of transistor T1 form a simple filter to prevent switch contact bounce from generating multiple clock pulses on pin 14 of IC1.
The clock pulse advances IC1’s count by one, so O0 goes low and O1 goes high. Therefore press switch S7 next, as it’s wired to output O1. The time required for capacitor C1 to charge to logic high level is the maximum time that can lapse between switches pressed. Otherwise, the counter will reset. When all switches have been pressed in the correct sequence (S2-S7-S3-S4-S5-S2-S2 as shown), output O7 (pin 10) of the counter goes high for about ten seconds. This output is fed to driver transistor T2 to drive the solenoid valve and open the lock.
Construction & testing
Assemble the circuit on a common PCB and enclose in a plastic cabinet. Connect the solenoid valve to the circuit using a flexible wire. While soldering, take care to avoid shorting. Use IC base for ease of troubleshooting. Connect the switches for opening the lock at the top of the plastic case.
The article was first published in November 2008 and has recently been updated.