Any change in voltage/current at the source is transmitted like a wave and reaches the receiver after wave propagation delay. This delay is dependent on transmission line parameters, that is, PCB tracks geometry and board material. At low frequencies of source signal, this delay is much smaller than rise/fall time of the signal. At sufficient high clock/signal edge rates, delay becomes comparable to the rise/fall time of the source signal/clock.
Transmission lines have an important characteristic called characteristic impedance (Z0), which depends on R, L, G, C and thus PCB tracks geometry and board material. Equations derived in transmission line theory using lumped parameter model show that at any instant of time, and at any point on transmission line, voltage/current values are obtained as the sum of a forward travelling wave from the source to the load and a reverse travelling wave from the load to the source. The reverse travelling wave is called reflected wave from the load.
If load impedance exactly equals Z0, amplitude of the reflected wave will be zero and there will be no reflected wave from the load. In this case, signals from the source are transmitted to the load without any distortion.
If load impedance does not equal Z0, there will be a reflected wave from the load to the source. This situation is called impedance mismatch. If there exists impedance mismatch at source side also, the reflected wave will be reflected back again from the source to the load. Thus there will be multiple reflections on both sides. Transmission line also attenuates the amplitude of forward and reflected waves along its length. Hence the amplitude of each successive reflected wave is reduced. These impedance mismatches and reflections cause the signal sent from the source to be distorted at the load end, giving rise to a phenomenon called ringing. This can be avoided by following appropriate resistor termination practices at the load side and/or the source side.
The rule of thumb for considering PCB tracks from a source to the load as transmission line is that the total propagation delay of the signal should be greater than one-sixth the rise/fall time of source pulses. This phenomenon is called signal integrity (SI). Software tools can be used to assess and fix proper values of terminating resistors and preserve signal integrity at the load end.
In the simple circuit of a source/driver delivering a signal to the receiver in Fig. 8, let us assume that the rise/fall time is such that wires need not be treated as a transmission line. Even in this case, if the frequency of current in the loop is sufficiently high, electromagnetic radiation from the current loop will give rise to disturbance in the operation of nearby electronic circuits. The current loop will also get affected by electromagnetic radiation from nearby circuits. This phenomenon is called electromagnetic interference. The EMI generated, or susceptibility to the EMI, is proportional to the frequency of current in the loop and loop area. Hence loop area needs to be minimised to minimise EMI.
As the source and receivers are components soldered on PCBs, and connecting wires are tracks on PCBs, care is to be taken during layout stage that send and return traces are nearby in single-/two-layer PCBs. If send and return traces are far away, it will result in larger current loop area, causing EMI problems at sufficiently high frequencies. In many cases, the return trace is nothing but signal ground. In a single-/double-layer PCB, every signal line should have ground trace just by its side—it is better to have the signal trace surrounded by ground traces on either sides.
If a PCB is very dense and doesn’t have space for so many signals and ground traces, multilayer PCB is a better solution. Alternate layers can be used for signal, ground and power planes—for example, layer 1 as signal plane, layer 2 as ground plane, layer 3 as power plane and layer 4 as another signal plane.
Here is how this concept works: High-frequency current always tries to follow a path that minimises the occupied current loop area because that path only provides minimum inductance/impedance. All signal traces in the signal plane can use any path below the ground plane for return current. This results in minimum loop area for all signal traces and thus minimum EMI/susceptibility. Signal traces in layer 4 use layer-3 power plane for high-frequency AC return currents. Many grounding and layer stacking schemes are available in literature to take care of these aspects.
If two signal tracks run very close to each other on a PCB, there will be capacitive coupling between them. High-frequency signal changes on one signal will get transmitted to the other signal because of capacitance. This phenomenon is called crosstalk.