- The newly launched clock-system-on-a-chip (ClkSoC) series by SiTime enables 5G vision of zero downtime, supporting better quality
- Includes MEMS resonator, filtering circuits, timing software and more for delivering higher performance
Delivers 10x higher reliability and resilience
Communications and electronics had previously implemented clock ICs with external quartz references for integrating multiple timing functions and to distribute clock signals. The company’s new, all-silicon clock architecture provides more integration by incorporating a MEMS resonator reference inside the package. More importantly, with SiTime’s MEMS technology, the Cascade clock-system-on-a-chip can deliver up to 10x higher reliability and resilience, enabling the 5G vision of zero downtime. Either standalone or together with SiTime’s MEMS TCXOs and OCXOs, the SiT9514x offers a complete timing solution for applications such as 5G RRUs, small cells, edge computers, switches and routers.
As 5G is expected to deliver 10 times faster speeds and 10,000 times more data, with 50 times lower latency and zero downtime, around 10 to 30 times more devices will have to be deployed; many of them in uncontrolled environments. Each of these connectivity gains is dependent on the accuracy, resilience and reliability of the system timing. Silicon MEMS timing technology inherently provides better reliability and resilience which is critical to support the quality of service planned for 5G.
Benefits of Clock-System-on-a-Chip
- Integrated MEMS resonator eliminates issues with quartz such as capacitive mismatch, activity dips, susceptibility to shock, vibration and EMI
- Four independent PLLs, with maximum flexibility to support time synchronization applications where multiple independent clock domains are required
- Up to 11 outputs with an operating frequency range of 8 kHz to 2.1 GHz, as well as a 1 PPS (pulse per second) output, for maximum frequency agility
- Programmable PLL loop bandwidth down to 1 milli-Hz for maximum filtering of wander or network noise in IEEE 1588 and synchronous Ethernet
- Fail-safe operation in case of input clock failures through faster hitless switching between four independent inputs. In such a situation, the device automatically switches to different input clock sources with minimum phase transient at the output, allowing the downstream PLL to remain locked, and the system to continue to operate reliably
- Excellent PSNR for highest performance in the presence of power supply noise
- Minimal external filtering circuits for a simpler design, space savings and BOM reduction
- Rich programmable features and configuration options: (1) Blank ISP (in-system programmable) devices provide maximum flexibility; (2) Pre-programmed devices enable system boot up without software configuration for maximum simplicity
- EVBs and TimeMaster
software enable users to map clock configurations and generate the scripts for software integration, which speeds development
“SiTime continues to expand our focus on the communications-enterprise market for many reasons. Our MEMS technology is well suited to solve the difficult timing challenges of emerging 5G infrastructure. This represents a large growth opportunity for SiTime that is complemented by production usage for many years,” said Rajesh Vashist, CEO of SiTime. “Today, our Elite Platform
The SiT9514x clock-system-on-a-chip family is sampling now. High volume production quantities will be available in Q4 2020.