It enhances accessibility and offers design flexibility to PolarFire FPGAs for hardware acceleration in edge compute systems
The demand for Field Programmable Gate Arrays (FPGAs) has increased, thanks to the need to combine performance with low-power consumption for edge compute applications and power-efficient accelerators while also providing flexibility and quick time to market. However, the majority of edge compute, computer vision and industrial control algorithms are developed in C++ by developers who have little or no knowledge of the underlying FPGA hardware, which poses a challenge to the accurate implementation of FPGAs.
Therefore to enable greater productivity and ease of design, Microchip Technology Inc. has introduced a High Level Synthesis (HLS) design workflow, called SmartHLS to its PolarFire FPGA families. Now C++ algorithms can be directly translated to FPGA-optimised Register Transfer Level (RTL) code.
Based on the open-source Eclipse integrated development environment, the SmartHLS design suite uses C++ software code for generating an HDL IP component that can be integrated into Microchip’s Libero SmartDesign projects, thus enabling engineers to describe high-level hardware behaviour than what is possible with traditional FPGA RTL tools. The design suite also reduces development time through a multi-threading Application Programming Interface (API) that executes hardware instructions concurrently and simplifies the expression of complex hardware parallelism as compared to other HLS offerings.
Only 10x fewer lines of code than an equivalent RTL design are required by the Smart HLS tool, which results in better readability, interpretation, testing, debugging and verification of the code. The tool also simplifies exploration of hardware microarchitecture design trade-offs and enables pre-existing C++ software implementations for use with PolarFire FPGAs and FPGA SoCs.
“SmartHLS enhances our Libero SoC design tool suite and makes the vast benefits of our award-winning mid-range PolarFire and PolarFire SoC platforms accessible to a diverse community of algorithm developers without them having to become FPGA hardware experts,” said Bruce Weyer, vice president of Microchip’s FPGA business unit. “Together with our VectorBlox
Developers can now design using the SmartHLS v2021.2 tool. It is available on the Microchip website, is part of the recently released Libero SoC V2021.2 design suite and can also be used as standalone software.
About the PolarFire FPGA Family
The low-power PolarFire FPGAs and FPGA SoCs help solve difficult edge compute system design challenges. The low-density additions to the FPGA family consume half the static power of alternatives in a small thermal footprint, reducing system costs and meeting thermal management requirements without forfeiting bandwidth. These new FPGAs as well as the SmartFusion 2 FPGA and IGLOO 2 FPGA are also supported by the new tool.