Synopsys recently announced its next-generation ATPG and diagnostics solution, TetraMAX II. It incorporates the innovative test engines unveiled at an earlier International Test Conference in October 2015.
Delivering an order of magnitude faster runtime, TetraMAX II cuts ATPG runtime from days to hours. This ensures that patterns are ready when early silicon samples are first available for testing. Additionally, TetraMAX II generates 25 percent fewer patterns, allowing IC design teams to shorten the time and lower the cost of testing silicon parts or, if required by specific market segments such as automotive, increase the quality of test without impacting test cost.
Reuse of production-proven ATPG interfaces ensures risk-free, easy deployment into design and test flows. TetraMAX II is built on new test generation, fault simulation and diagnosis engines that are extremely fast. These also feature exceedingly memory efficiency and high optimization for generating patterns. The solution is capable of executing fine-grained multi-threading of the ATPG and diagnosis processes. These innovations lead to significantly fewer test patterns and cut ATPG time from days to hours.
Memory management in the TetraMAX II
Memory efficiency of TetraMAX II enables utilization of all server cores regardless of design size. The reuse of design modeling and rule checking infrastructure, as well as user and tool interfaces, ensures designers can quickly deploy TetraMAX II risk-free on their most challenging designs.
“Designers worldwide rely on Synopsys’ synthesis-based test solution to achieve the highest test quality on their most challenging designs,” said Antun Domic, executive vice president and general manager for Synopsys’ Design Group. “TetraMAX II demonstrates our commitment to continually deliver innovative and groundbreaking test technologies and addresses our customers need for faster ATPG and diagnostics as well as reduced silicon test time.”
The Synthesis-Based Test Solution
The Synopsys synthesis-based test solution is comprised of SpyGlass DFT ADV testability analysis, DFTMAX, DFTMAX Ultra, TetraMAX I and II for power-aware logic test and silicon diagnostics; the DesignWare STAR Hierarchical System for hierarchical test of IP and cores on an SoC; the DesignWare STAR Memory System solution for embedded test, repair and diagnostics; the Yield Explorer tool for design-centric yield analysis; and the Camelot software system for CAD navigation.
Synopsys’ test solution combines Design Compiler RTL synthesis solution with embedded test technology to optimize timing, power, area and congestion for test as well as functional logic, leading to faster time-to-results. The test solution delivers tight integration across the Synopsys Galaxy Design Platform, including Design Compiler, IC Compiler II place and route tool, and PrimeTime timing signoff, to enable faster turnaround time while meeting both design and test goals, higher defect coverage and faster yield ramp.
Automotive safety compatibility with ISO 26262
“Tool qualification according to ISO 26262 is an important contribution to increased engineers’ confidence in the EDA software tools they use to develop automotive ICs targeted at electronic safety systems,” said Gudrun Neumann, product manager of Functional Safety Software at SGS-TÜV Saar GmbH. “Satisfying the ISO 26262 for the most stringent ASIL D applications enables IC design teams to accelerate the overall functional safety certification requirements for their products. TetraMAX II ATPG complies with the ASIL D safety requirements for software tools used in the development of safety-related electronic systems. SGS-TÜV Saar’s certificate for TetraMAX II is based on a successful functional safety evaluation of validation processes against the requirements of ISO 26262.”
“Synopsys’ automotive IC customers worldwide have trusted TetraMAX ATPG to deliver the best test quality and lowest test cost for their most complex designs,” said Bijan Kiani, vice president of marketing in Synopsys’ Design Group. “Our new TetraMAX II ATPG solution reinforces our commitment to helping automotive IC design teams accelerate their manufacturing test development by reducing ATPG runtime from days to hours and lower test costs with 25 percent fewer patterns. For automotive IC applications, TetraMAX II provides the opportunity to increase test quality with multiple fault models, without significant impact to test costs and test generation time. In addition, certification for TetraMAX II contributes to meeting their functional safety requirements related to compliance of the ISO 26262 standard.