Automotive SoC With CNN Accelerator Cores And ASIL D Control

Delivers 60.4 TOPS and 13.8 TOPS/W, processing complex tasks for autonomous driving systems on a single chip

Renesas Electronics Corporation has successfully developed processor technologies for automotive systems-on-chip (SoC) that can be used for optimising both performance and power efficiency of advanced driver assistance systems (ADAS) and autonomous driving (AD) systems while supporting a high level of functional safety. 

Applications such as next-generation ADAS and AD systems require outstanding deep learning performance of 60 TOPS or even 120 TOPS alongside power efficiency. Besides, since signal processing from object identification to the issuing of control instructions constitutes a bulk of the processing load in AD systems, achieving the functional safety equivalent to ASIL D is a pressing issue. Therefore the new technologies meet these needs, including a hardware accelerator that delivers outstanding CNN processing performance with superior power efficiency.

The newly-developed technologies used in the R-Car V3U SoC are:

• High-performance CNN hardware accelerator with superior power efficiency

 As the number of sensors utilised in next-generation ADAS and AD systems increases, more powerful processing performance is required. There is also a need to reduce the heat generated by power consumption to make possible electronics control units (ECUs) that are air-cooled, bringing weight and cost advantages. Therefore the new convolutional neural network (CNN) hardware accelerator core comes with superior deep learning performance and implements three such cores, in a high-density configuration, on the R-Car V3U. 

Additionally, the R-Car V3U has 2 megabytes (MB) of dedicated memory per CNN accelerator core for a total memory of 6 MB. This reduces data transfers between external DRAM and the CNN accelerator by more than 90 per cent and successfully achieves a high CNN processing performance of 60.4 TOPS with best-in-class power efficiency of 13.8 TOPS/W.

• Development of safety mechanisms for ASIL D systems capable of self-diagnosis

 The ISO 26262 automotive functional safety standard specifies numerical targets (metrics) for various functional safety levels. The metrics for ASIL D, the highest functional safety level, are 99 per cent or above for the single point fault metric (SPFM) and 90 per cent or above for the latent fault metric (LFM), which means that an extremely high detection rate is required for random hardware failures. 

Also, due to the high level of involvement in vehicle operation of systems such as next-generation ADAS and AD systems, automotive SoCs have overall incorporated more functions subject to ASIL D requirements. Safety mechanisms for fast detection of and response to random hardware failures occurring in the SoC have been developed, allowing reduced power consumption and a high failure detection rate. The incorporation of these mechanisms into the R-Car V3U is expected to bring the majority of the SoC’s signal processing into achieving the ASIL D metrics, which is capable of independent self-diagnosis and reduces the complexity of fault-tolerant AD system design.

• Support mechanism for freedom from interference (FFI) between software tasks

 Achieving freedom from interference (FFI) between software tasks is an important aspect of meeting functional safety standards. When software components with different safety levels are present in the system, it is essential to prevent lower-level tasks from causing dependent failures in higher-level tasks. FFI should also be ensured when accessing control registers in various hardware modules and shared memory. For this, an FFI support mechanism has been developed that monitors all data flowing through interconnects in the SoC and blocks unauthorised access between tasks. This enables FFI between all tasks operating on the SoC, making it possible to realise an SoC for ASIL D applications capable of managing object identification, sensor fusion with radar or LiDAR, route planning and issuing of control instructions with a single chip.

Renesas presented these achievements at the recently concluded International Solid-State Circuits Conference 2021 (ISSCC 2021).

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