But what was Berkeley RISC?
In the past, CISC microprocessor cores like Motorola 68000 used only a subset of the available instruction set; therefore most of the decoding circuitry for the never-used instructions was wasted. But in RISC, CISC was replaced with multiple registers to speed up the execution since access to these registers would take less cycles than memory access needs, outperforming CISC.
Considering the case of ADD instructions in which CISC would appear in different formats where one would be meant for adding the numbers in two registers and placing the result in third, whilst the other would allow to add two numbers stored in the main memory and store the result in a register, offering wide variety of instructions to perform the required operations and providing several options as operands.
But in the case of RISC designs, the ADD would always take registers as operands, which creates a necessity for the programmer to write additional instructions to load the values from memory whenever required. Now, the Berkeley RISC was able to provide good performance utilising pipelining and register-windowing technique. In register windowing, the CPU contains a large number of registerss around 128, together called a register file, whilst the group of eight registers is called a window. But a program can only use one window, thereby allowing fast procedure calls. The call simply moves the window down to the set of eight registers used by that procedure and the return moves the window back.
After that time, RISC has seen a lot of developments proving its simplicity over CISC. Here are some of the features of RISC:
1. Large general-purpose 32-bit register banks
2. Fixed 32-bit instruction size
3. Hard-wired instruction decode logic instead of microcoded ROMs
4. Single-cycle execution is possible
5. Pipelined execution
6. Easier to prototype
RISC features can be introduced in CISC processors but would require much more hardware. A typical RISC architecture consists of a large uniform register file, load and store architecture, simple addressing modes and uniform fixed-length instruction fields. Due to this characteristic, we achieve high performance, low code size, low power consumption and low silicon area.