An ARM processor consists of 31 general-purpose 32-bit registers. Sixteen registers, namely R0-R15, are visible, which means they can be modified by the user whereas other registers help to speed up the exception process. Some registers play some special roles, like R14 acts as a link register (LR), R15 acts as a program counter (PC) and R13 acts as a stack pointer.
There are seven modes of operations as shown in the box (on previous page). Their modes are categorised as user mode, privileged mode and exception mode. User mode is a normal program execution mode in which the system resources are unavailable. If some exception occurs, then the mode is changed to the exception mode. In exception mode, all system resources are available.
There are two important registers in ARM, namely current program status register (CPSR) and saved program status register (SPSR). CPSR is similar to PSWR register in 8051 microcontroller which indicates some important flag bits like carry bits and zero flag bits as shown in Fig. 1, whereas SPSR is used in exception modes. Whenever exception occurs, the contents of CPSR are copied to SPSR. The organisation of registers in an ARM processor is as shown in Fig. 2.
The ARM architecture has evolved through many stages; the smartphones employ ARMv5 architecture and the later releases. Hardware floating-point unit (FPU) is the major change brought in ARMv7 to provide more speed than the software-based floating point. Even DSP instructions were added to the set to improve the ARM architecture for use in digital signal processing (DSP) and multimedia applications. In ARMv7, even the Thumb-2 feature, to obtain code density as Thumb and performance as ARM instruction set, was added that extends 16-bit Thumb instruction set with 32-bit instructions, producing instruction sets of variable lengths.
A new ‘unified assembly language’ (UAL) support is provided to generate Thumb-2 or ARM instructions, whichever is required from the same source code. The new ARMv8 has undergone a considerable change by using 64-bit architecture and cryptography instructions supporting AES and SHA-1/SHA-256, and even allows 32-bit applications to be executed. An optimised ARM smartphone block diagram is shown in Fig. 3 (Source: www.arm.com).
Therefore this ARM architecture with brilliant features is widely adopted by many organisations (more than 2500 organisations are licenced with IP), as a result of which it is the world’s leading semiconductor IP supplier, having over 40 billion ARM processor based chips shipped to date, providing each user with smooth experience. So with ARM and its ever-improving architecture, the future of computing devices not only has a better scope by being cost-effective, but they also have plenty of features to offer.
The authors are BE final year students at NMAMIT, Nitte