Testing High-Speed Memories


Crouch adds, “Once production has hit its stride, memory tests are performed again on boards that fail the manufacturing test suite and do not qualify for release to the market. The only intent here is to determine whether the failures were a result of environmental conditions, random defects or some systematic problem in manufacturing that is affecting yields. During post-production phase of the life-cycle, or when systems have been installed in the field, memory tests are performed to troubleshoot malfunctioning systems and maintain user satisfaction. The two main goals during this phase are to identify any and all reliability concerns such as memory chips or board structures that fail earlier than expected and, second, to identify changes that might make the board design or the component selection better suited to deployment. The key aspects of post-production testing are to collect performance and reliability data in a real world environment and to resolve the collected data to any sources of faults or failures that generated it.”

Samant says, “Memory testing today requires high channel count, high-speed dynamic data and multiple control channels each with per pin parametric measurement capability. It also requires per pin programmable voltage levels and the ability to independently source or sink current. The tests also require sophisticated timing engine with sub-Hertz frequency and per pin timing resolution in the range of pico-seconds. Today’s tests also require the ability to perform inline processing between the stimulus and response and real-time performance.”

Future of high-speed testing
Today, circuit boards have complex memory architectures that are becoming harder to test due to their high speeds, high rate of data transfers on memory buses, complex protocols and loss of test points on boards where a test probe can be placed. Coverage from intrusive probe-based methods of memory test and validation, such as oscilloscopes and in-circuit test (ICT) systems, is rapidly eroding. These legacy test methods are quite challenged by today’s aggressive test goals.

Bhatia remarks, “The high-speed memory field has grown in speed by leaps and bounds. DDR1 used to operate at 200MT/s or 100MHz clock rate, whereas GDDR5, the high-speed memory for graphics, operates at 7GHz clock speeds. There is also a trend towards over-clocking the memory designs beyond their specs. For example, DDR2 is specified till 800 MT/s, whereas it is operated at 1 GT/s. DDR3 is defined till 1600 MT/s, whereas actual operating speeds cross 2 GT/s. In addition, the packaging of high-speed memories has also changed over the years with variants of DDR found in DIMM and SO-DIMM variants.”

Kenneth Johnson, director of marketing, Teledyne Lecroy, says, “Each new generation of DDR memory has doubled the clock rate and reduced the voltages used. DDR test requirements, aside from probe and oscilloscope bandwidth requirements, haven’t changed much from DDR1 to DDR3. DDR4, due to its higher transfer speeds, requires new jitter and eye diagram tests that are similar to what has been utilised for high-speed serial data electrical physical-layer validation, namely, eye diagrams of clock/data signals and extrapolated total jitter (Tj) calculation with random jitter (Rj) and deterministic jitter (Dj) separation. Other memory specifications are the adoption of smaller footprints and packaging. These trends make test and validation much more difficult as probing becomes limited to outside the memory package.”

Sai Venkat Kumar B, Country Marcomm, Tektronix says, “With the increase in data rate, memory density and power requirements, memory testing has become more challenging. We now have 120 plus tests to perform as per JDEC for DDR4. Performing these tests in conformance with the specifications presents a host of challenges that can be a complex and time-consuming task.” He adds, “One of the first obstacles to be overcome in memory validation is the issue of accessing and acquiring the necessary signals. The JEDEC standards specify that measurements should be made at the BGA ballouts of the memory component. FBGA components include an array of solder ball connections that are, for practical purposes, inaccessible. Nexus Technology’s patent pending EdgeProbe design removes mechanical clearance issues as the interposers are targeted to be the size of the memory components themselves. Embedded resistors within the inter-posers place the scope probe tip resistor extremely close to the BGA pad, providing an integrated scope probe on all signals.”

The author is a tech correspondent at EFY Bengaluru


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