• Logic analysers
• Pulse pattern generators
• Arbitrary waveform generators
• Semiconductor parametric analysers
• EDA tools
• Design-for-testability tools[/stextbox] If the chip fails, a series of tests are performed to locate the fault. This is done by the chip designer himself. Veerappan says, “Sometimes we cut open the chip to find the problem and inform the designer where the design went wrong.”
Logical tests help in detecting where the input and output mismatch. “These digital test results help to find the point of failure and do detailed analysis,” explains Varambally. He adds that checking the nodes of abnormal current and voltage, waveform shapes and signals and comparing them with the expected values helps in debugging.
Even standard test equipment like logic analysers and pattern generators have evolved over the years to help ensure that there is a smooth handover from design simulation to actual device test. Kumar explains, “This is achieved by providing linkage for accepting test vector inputs from design tools. Designers can create test vectors in VHDL, etc, and the same can be imported into pattern generators to actually generate and apply the same to the ICs as digital stimulus.”
Design for testability
You must be able to test every design to ensure the intent of the design. “If the design is not testable, it may be very difficult to find the fault after packaging. This involves cost and time,” explains Veerappan. There are different software tools available from companies like Cadence and Synopsys to design for testability.
Varambally explains, “Let’s say there are millions of transistors, but only hundreds of pins. Practically, you should be able to test any chip failing through only these pins. The concept of design for testability applies to testing of all the transistors or different sections of the chip.” There are different test nodes created to test various sections of the IC.
Advanced test equipment are very expensive. So the time involved in testing each chip is very critical. “Design for test helps reduce the time to test one chip, thereby increasing the utilisation factor of the tester. So you need to design the chip such that your testing time comes down,” explains Varambally.
The cost of a chip design is millions of dollars, which also includes the cost of test. To minimise the cost and perform the test efficiently, sometimes an extra circuit is added to perform tests.
Varambally says, “We inculcate all the testing features in the design stage itself. For example, we can put a small extra structure along with the circuit, like a small block. Although there is a small price associated with this extra piece of silicon, it will reduce the testing time and cost. So it is okay to pay a bit of silicon fully for testing.”
Embedded selftest inside the chip itself is a logical and viable future solution for complex SoC designs that saves test development cost and reduces the load board and ATE system complexity.
Sabapathi S.R., chief executive officer, Qmax, says, “The built-in selftest can be commanded by simple low-cost JTAG interface. This will cover the functionality of the device. Henceforth ATE test will be much simpler and in some cases limited to DC and AC parametric tests alone. The resultant savings easily justify additional silicon block embedded into the chip.”
After the silicon has passed the tests and the chip is sent for mass production, every chip produced undergoes similar tests. Every chip is tested for its functionality and characterisation. Testers are preloaded with test programs to test the ICs. There are tools for signal integrity and thermal management tests.
A go-no-go test is performed on every chip in big test assemblies called ATEs or testers. Veerapan explains, “There are test load boards to load the chip into the tester. The test program is customised. Every pin of the IC has to be activated by some signal, and the tester will send the signal and receive an output, which will then be compared with the expected output. So, basically, the tester simulates the test as if the end customer is using the chip.”
Designing of test load boards is another critical area requiring skilled test engineers. Varambally adds, “Another key consideration is that one tester can test only one IC or range of ICs of a particular category. There is no universal tester that can be used to test all the ICs in the world.”
For better and faster testing
The design and test methodology has to evolve with the increasing complexity of silicon design. “Testing is becoming an integral part of design. Unless you have very good test methodology built into your design tool and at design stage, it will lead to critical problems. So designers and test engineers have to work hand-in-hand. Unless these guys work together, testability will become a problem later,” claims Bhardwaj.