7. Finding true-3D IC manufacture very costly, Intel has started producing chips based on its novel Tri-Gate technology that makes use of 3D transistors. This technology is apparently just 2 to 3 per cent costlier than traditional designs while offering many of the benefits of 3D ICs.
Speaking at the Intel Developer Forum this year, Mark Bohr, Intel’s Process Guru, revealed that Intel is still studying ways to implement true 3D ICs, but sounded sceptical about the chances of the firm implementing it.
“Having the technology and having a cost-effective solution are two different things,” Bohr said. “We can do 3D chip stacking, but I think the added cost is still a bottleneck.”
Bohr added that multi-chip packages and package-on-package technologies are already in wide use and appear to be far more cost-effective than 3D chip stacking.
“The problem with 3D stacking is that it may be a viable solution for a 1-watt product, but it’s not an acceptable solution for a 30- or 40-watt product because you can’t dissipate all of that heat out of the package,” Bohr said.
8. Meanwhile, IBM is planning an alternative route for manufacture of 3D ICs. It believes that the best way is to glue together entire wafers with a thermal adhesive it has developed in collaboration with 3M. Apparently, doing the tricky alignment once and then dicing apart the wafer might be less expensive than stacking tiny chips after they have been diced out of the wafer.
9. Hewlett-Packard is working to create stackable 3D chips that communicate using built-in microscopic lasers. These chips consume 80 per cent less power than traditional chips and are targeted for release in 2015.
What design tools are available to start using 3D chips?
Peckham pushes designers to try 3D, saying, “3D chips enable designers to create system-level designs with unprecedented levels of integration, leading to higher performance and lower power consumption than has ever been possible before.”
Depending on the chips they plan to use, designers can choose from various toolkits to design their computing systems using 3D chips. Some experts feel that a toolkit need not be purely 3D, but a generic one which is 3D-aware.
[stextbox id=”info”]3D chips enable designers to create system-level designs with unprecedented levels of integration, leading to higher performance and lower power consumption than has ever been possible before[/stextbox]
To improve designers’ productivity with its all-programmable devices at 28nm and beyond, Xilinx has developed a next-generation design environment and tool suite called Vivado. Without this design suite, design teams could not effectively leverage Xilinx’ 3D ICs. The Vivado Design Suite further improves the quality of designs by up to three speed grades, cuts dynamic power consumption by up to 50 per cent, improves routability and resource utilisation by over 20 per cent, and speeds time to integration and implementation as much as fourfold.
Design automation leaders like Cadence, Mentor Graphics, Synopsis and Calypto have several tools for 2.5D as well as 3D IC design. Synopsis has teamed up with TSMC, while Cadence has collaborated with Taiwan’s Industrial Technology Research Institute to design next-generation 3D ICs.
TSMC also works with tools from Apache Design and its parent company ANSYS for its 20nm and stacked die reference flows, as these tools address thermal analysis, run-away and thermal-induced electromigration, as well as power, noise and reliability issues. The tools include RedHawk, Totem, Chip Thermal Model, Sentinel-TI, Slwave and Icepak. It is important to use tools that address multifarious issues rather than focus only on performance aspects.
The author is a technically-qualified freelance writer, editor and hands-on mom based in Chennai