7nm IC Technology Trends And Challenges (Part 2 of 2)

By V.P. Sampath


Transistor options

You must select the right transistor architecture for 5nm. Today, there are two leading options: finFET and nanowire FET. Scaling FinFET to 5nm is challenging. In a 5nm FinFET, for example, fin width is projected to be 5nm, which is supposedly the theoretical limit for this structure. That is why chipmakers are exploring nanowire FET.

Nanowires have good electrostatics. But these come with other issues such as device width of nanowires and how much current you can get out of devices. Those are the areas that people are flushing out.

Mask making

In process flow, meanwhile, photomask manufacturing is one of the first steps. As before, lithography determines mask type and specs. So if 5nm happens, the photomask industry will likely need to develop masks for two lithography types—optical and EUV lithography. Making an optical mask will be daunting at 5nm. Bringing up EUV mask line is also difficult, as these are very different from 193i masks in many ways.

Because it is such a massive change, it will have a huge impact on features or capabilities of every product in the supply chain. This includes resists, masks and pellicles, as well as equipment like e-beam writers and even software.

On EUV mask front, the industry is making progress in some areas, but not in others. Mask blank inspection is a bright spot. EUV mask inspection and pellicles are question marks. For 5nm, though, mask write times will be the biggest challenge. Today’s single-beam e-beam tools are unable to pattern complex masks fast enough and in a cost-effective manner.

There is a solution. Two groups, IMS/JEOL duo and NuFlare, are separately working on a new class of multi-beam e-beam mask writers. The tools, which promise to accelerate write times, are expected to ship soon. Reports have surfaced, however, that development of these tools is taking longer than expected due to technical issues. Any disruptive new technology like this will take time to mature before it reaches high-volume production.


After the mask is made, it is shipped to the fab. The mask is placed in a lithography tool. Then, the tool projects light through the mask, which, in turn, patterns images on a wafer. Needless to say, patterning is one of the big question marks at 5nm. For this, chipmakers hope that EUV is finally ready for 7nm and 5nm. This, of course, depends on the status of the power source, resists and mask infrastructure.

In theory, EUV will simplify the patterning process, thereby reducing cost. But even if EUV happens at 7nm and/or 5nm, chipmakers would require a form of multiple patterning.
Here is a worse-case scenario. If EUV misses the window at 7nm and/or 5nm, chipmakers will hit a roadblock. It is possible to extend today’s 193nm immersion to 7nm and beyond, but chip-manufacturing costs will become even more astronomical.

A 5nm process with EUV should be cheaper than a 5nm process without it, but either version may be so expensive that increasingly fewer companies could afford it. At 5nm, though, chipmakers would likely implement a mix-and-match strategy. EUV will not mean the end of multi-patterning.

EUV is ready for primetime, and you will most likely see a mix of 193i single- and multi-patterning, single-pattered EUV and potentially multi-patterned EUV. It will be layer-specific. Some of the very simple, large-dimension layers will still be printable with single-patterned 193i. Double-patterned 2LE 193i will still be cheaper than single-patterned EUV. Potentially, even triple-patterned 3LE 193i may be cheaper for some layers.

Self-aligned double patterning will also be cheaper than single-patterned EUV. EUV should be cheaper than 4LE or 5LE. So it would be used in place of those on appropriate layers. It may be used in place of SAQP alternatives as well. The most critical of layers may have dimensions so tight that it would require double-patterned 2LE EUV.

There are other issues as well. To extend EUV beyond 7nm, the technology may require a high numerical aperture lens as a means to boost magnification of the scanner. For this, ASML is developing an anamorphic lens for EUV. The two-axis EUV lens would support eight times magnification in the scan mode and four times in the other direction. It would support 0.5 to 0.6 numerical apertures. EUV scanner could take a throughput hit. It would expose the wafer at only half the field size, as opposed to full-field sizes with today’s EUV scanners.

V.P. Sampath is a senior member of IEEE and a member of Institution of Engineers India. He is a regular contributor to national newspapers, IEEE-MAS section, and has published international papers on VLSI and networks


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