Disruptive Technologies: Arriving At A Specification Document… Is The Biggest Challenge

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Q. Are there any additional challenges that can be attributed exclusively to the disruption angle?
A. Managing design feasibility, processor/component and cost parameters and arriving at a balance is a challenge on its own.
Another difficulty comes while integrating analogue sensors with the board. While working with chips that are new in the market, there is always a risk of finding bugs or errors. You may even run the risk of a certain component not being ready for sale in the market when you go in for manufacturing. This is where the time-scale factor comes into play.

Q. Has there been any unique situation that you have come across?
A. We had to debug and fix a thermal issue on one of our customer’s hardware. This was an x86 based design, running Windows.

The board used to crash after some time when exposed to temperatures above normal room temperature. Even though the board was designed for extreme temperatures, it was not working as expected.

We had to do a detailed thermal analysis, including thermal simulation using standard tools and also several tests inside a thermal chamber to identify and fix the problem, by re-designing the heat-sink. In fact, we had to reduce the heat-sink area to fix this issue, whereas, generally, fixing thermal issues calls for increasing the heat-sink area.

Q. With challenges that come with working on disruptive technologies, how do you approach a project in this domain?
A. First thing we need is good engineers with the latest skill-sets and those who understand latest technologies and have the passion to work in these fields.

We also require good lab infrastructure to test designs and good ecosystem that supports fabrication and assembly of boards.

We have a strong team in place already, most of them handpicked from the industry, and we regularly recruit top-notch engineers. We make sure that they understand the latest technologies and are capable of facing the many design challenges.

We have a good lab infrastructure and can do most design qualification tests in-house. We use external labs when it comes to EMI/EMC tests. We also make sure our designs are first-time right by doing multiple rounds of reviews at all stages of the design cycle.

Q. Would you share some ways of tackling the space-size challenge?
A. With the shrinking device sizes, we end up putting many features in a very small size. Component selection becomes an important criterion whenever there is a space-size challenge. Optimised component placement and use of HDIs on the PCB help in arriving at the target size. PCB features such as trace width, via size, trace-trace clearance, have to be extremely minimised to achieve some form-factor requirements.

However, there is a limitation in manufacturing these boards in India as fabricators do not have sophisticated equipment to build these.

Cooling such high-density designs packed in a small area would be another challenge.

Q. How do you manage thermal issues in fan-less designs?
A. During the design phase, extensive thermal analysis is done starting with component-level heat calculations, followed by board-level tool based thermal simulation to estimate the amount of heat generated at maximum power.

Proper copper areas on the board, appropriate heat-sink designs and selection of right thermal interface material help keep the design cool even at extreme temperatures. In some cases, the enclosure also needs to act as a heat dissipater. The choice of enclosure material and proper thermal design becomes critical here.

Q. What compromises have to be made to comply with EMI/ EMC tests?
A. Appropriate ground references and proper return paths help in reducing electromagnetic emissions, which may add additional board area or number of layers.

Circuits may demand additional devices for ESD and surge protection. Chassis based systems may need gasket or copper strips to seal gaps to prevent radiations, which adds to the cost of the system.

Getting the design to pass EMI/EMC certifications might involve multiple re-spins, which impacts the development time and also adds to the development cost.


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