EDA Becomes Interactive With 3D Rendering and Routing Solutions

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Improving the finer points

Making the interface attractive and easy to use certainly helps and the industry has been working on this direction as well. Deepak says, “In the last year we have focused on making our tools more user friendly.”
With the large number of available components and the minute changes from one component to the next, accurate documentation is also a necessity. Hence, “efficient documentation tools are becoming a necessity,” says Tamanna. The updated tools have automatic schematic and PCB generation, which reduces error due to human intervention.

Taking on the challenges

Certain challenges faced during development can be during designing the circuit, mask preparation, testing the circuit and so on. For circuit designing, Rossi explains it as, “Once the objective is ‘within reach’ we ‘hold’ placement and routing, and systematically ‘change’ the gates: same footprint, different timing, power, temperature inversion point.”

Routing the circuits

Nowadays, hundreds of multi-million instances are packed in a single SoC. It’s practically impossible to do custom / manual routing and hence designers use the EDA tools to do auto routing. According to the Cadence design team, the routing can take anywhere from a few few hours to days, depending on the complexity of the circuit. For such complex SoCs which have billions of transistors, extracting the resistance and capacitance is a Herculean task.  Commercially available field solvers do the things automatically once the placement and routing is done during the design phase.


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The primary challenge in mask creation is for semiconductor manufacturers to continue scaling at and below 16/14 nm using 193 nm ArFi lithography equipment. “Until next generation lithography equipment (EUV) is available for production, manufacturers must find techniques to print smaller and smaller geometries with existing equipment,” says Tom Ferry, VP of marketing, silicon engineering group, Synopsys.
He further adds, “Computational techniques modify the design layout to create mask designs that enable lithography equipment to produce patterns on the masks that accurately represent the layout (designer intent).”

Verification and Synthesis

For many years, designers exclusively relied on stuck-at automatic test pattern generation (ATPG) patterns to test ICs. Because delay faults caused by opens and shorts occur more frequently than stuck-at faults, designers gradually began to employ transition delay ATPG patterns to improve defect coverage and lower defective parts per million (DPPM).
According to Chris Allsup, technical marketing manager, sr. staff, RTL synthesis and test automation, Synopsys, “At advanced nodes, process variations give rise to increasingly subtle physical defects that require additional patterns that target more complex failure mechanisms such as partial shorts and partial opens.”
The RTL netlist, in Verilog format is now accompanied by a power intent description, in IEEE 1801 “UPF” format, and logic synthesis has been upgraded to understand power and ground, and to perform optimizations taking into account increasingly complex concepts, such as power/voltage/shutdown islands.

Could there be some database issues?

With the number of EDA tools, the compatibility among tools is another parameter to be considered. On the one hand files from one tool should be able to work with other systems in order for designers to have maximum ease of transition whereas on the other, tools have to be lightweight in order to work efficiently. Rossi puts to rest the database debate with, “There are no simple ‘databases’ in EDA, but rather efficient binary dumps on disks of the in-memory data representation/infrastructure of different classes of tools.”

How would the evolution go from here?

“Today, there is not a “solution of continuity” between our logic synthesis and our place-and-route tools,” adds Marco-Casale Rossi. “Moving forward, the border between logic synthesis and place-and-route will blur, and possibly disappear.”
Chip design is a constant battle against rising process and functional complexity on the one hand, and reducing time to market on the other. Additions like the 5g library for system design according to Deepak, helps innovation in technology as well.
We can hopefully look forward to a design environment that includes the validation of IP, libraries and foundry technology data at the beginning of the process. Support for standard yet adaptable design flows and insights into key project metrics throughout can ease the job of getting chips out of the door and into customers’ hands.



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