Design tool vendors often get to play with technology nodes long before the rest of the world even know these exist. In this interview, we sit down with a thought leader in the electronics design automation industry to get a glimpse of what is coming up. Walden C. Rhines, chairman and CEO of Mentor Graphics, speaks with Dilin Anand of EFY
A. There are three big things happening. First, we are seeing the most prolific new technology nodes in our recent history.
Second, we are seeing new types of tools coming up in the automotive sector to solve new problems in the value chain.
Finally, digital chips have grown so big that engineers are facing challenges with their verification.
Q. Where have we reached with process nodes in the semiconductor industry?
A. We have seen the best advances in technology nodes in the last few years, whose effects will ripple across the entire electronics industry. Semiconductor vendors are ramping up development on chips based on 28nm, 20nm, 14nm and 10nm process nodes. Looking at the future, we are also working with design tools for the next-generation 7nm process node.
Q. What are some challenges that are being faced with the next generation of process nodes coming in?
A. Every generation has new physics that we have to worry about. For example, Calibre PERC tool is used to help solve the effects of electro-migration, as the current drags the metal along with it. This could go on and, if undetected, cause the wire to fail.
When we reach nodes after 10nm, the industry could move away from silicon. In 7nm, for example, indium-gallium-arsenide (InGaAs) could be part of the flow that we use to build new models. Work on design tools and on calibre rule decks to check those tools always happens earlier, and we are currently working on 7nm and 5nm nodes.
Q. What are some of the biggest challenges that can be expected in 7nm nodes?
A. One of the biggest problems with 7nm is that, because extreme ultraviolet will not be available at the time of introduction, foundries will have to use triple etching or triple patterning, or even quadruple!
Self-assigned double patterning is another technique that could be used.
All these require a more complex process, but it also requires the designer to take into account the effects caused by these. For example, a given etching might be defined in one layer, then another and so on, but it would ultimately be affected by the layer being etched.
Q. Could you tell us about some benefits that are enjoyed by today’s design tool users?
A. Companies have discovered in the past year that, by using Tencent yield enhancement, they can save tens of millions of dollars in cost of components, by rapidly identifying defects in the layout that affect their yield. They are able to analyse every chip that fails in test and compare it to the layout. This lets them figure out if it is a systematic or random issue, following which maths tools analyse and bring out correlation.
The next is that, without emulation, most networking companies would have been unable to continue as complexity of data networking is now so great that simulation is no longer possible.
Q. Are there any similar examples from the foundry side?
A. The foundry industry has found that, by requiring their customers to use a tool called Calibre PERC, they could assure that customers’ designs had protection for electrostatic discharge (ESD).
What previously happened was that every customer had his or her own different techniques to check. As a result, when wafers came back, ESD destroyed those wafers and these customers would tell foundries that the yield was low.
Q. What are the new tools coming up in the automotive sector?
A. New tools are now available that enable embedded software development capabilities for automotive design using standards such as automotive open system architecture (AUTOSAR). We are now also seeing new analysis tools for connectivity in a car, as well as tools for documentation and even to help technicians with wiring.
For electronics manufacturing services, design for manufacturing and assembly markets we see that, as design complexity increases, these companies start facing issues in library management. So that is another area where problems can be solved.
A. Engineers working on big digital chips now have to adopt emulation to just handle the enormous amount of verification needed. To help in solving these new challenges, we saw the introduction of integrated simulation and emulation as well as a big advance in power analysis introduced in cooperation with ANSYS.
Additionally, it is now also possible to design for test in the emulator itself.
Q. What is the roadmap for system design tools, and how does it compare to chip design tools?
A. Traditional chip design tools are growing at the same rate as the semiconductor industry. However, since system design is at an early stage, it is growing at two to three times as much.
Looking at the systems-side roadmap, we can expect design tools made to handle the integration of optics and computer systems, backplanes and printed circuit boards.