The Latest in Chip Design


Q. What are the latest concerns for EDA players vis-a-vis chip design?
Saugat Sen: One of the biggest challenges EDA companies face today is the accelerated pace of advanced node introduction. The pace of movement from 20nm, 16nm/14nm and on to 10nm is very challenging, from both the technology development standpoint and from the deployment angle. Gaining early deployment experience via test chips with major partners has become an indispensable part of the new node
deployment-planning process.

Wesley Ryder: It is quite hard to think of concerns around EDA and chip design. Looking back, technology advances always created concerns but clever designers and software engineers continued to overcome them, and there is no reason why they will not continue to do so in the future. Fostering and finding top talent is always high on Mentors’ agenda. Tools are important, but it is the people and relationships that make the real difference in a company.

Sushil Gupta: Complexity management and successful IP re-use are the two major concerns that are high on the list of most EDA vendors. Both these concerns can cause substantial issues for a system-on-chip (SoC) project concept, and hence, EDA players should be focussing on these issues.

Vinayakam SUbramaniam: Chip design cycles are getting shorter while the chips are getting more complex. Add to this the impact of the package and PCB on the chip’s performance, and it becomes clear that first-time system success (chip+package+PCB) is critical.

Q. Can you talk about some of the latest trends that you have witnessed in this field, which you believe are here to stay?
Saugat Sen: Re-use and use of third-party IP have become standard business practices for many semiconductor companies, and this has led to greater awareness about the importance of IP re-use strategies. The critical factors driving IP re-use are two time-to-market concerns and the rising complexity of SoCs in production today.

Wesley Ryder: Focus on low power is a trend that has come under the spotlight and is certainly here to stay. An increasing number of processing engines on SOCs drive the need for more power compared to the ideal—a topic deeply discussed in the International Technology Roadmap for Semiconductors (ITRS) documents. With multiple devices placed on boards, it is common to find PCBs consuming several hundred watts and systems much more.

Sushil Gupta: IP re-use is here to stay. The IP market will need to go through some maturity for it to continue to grow, however. The movement to higher levels of abstraction (to deal with complexity) is also real and growing. The choice of a place and route tool used to have a substantial impact on a project’s success. Going forward, the tools used for register transfer language (RTL) and architectural design, as well as the choices for IP, will have the biggest impact.

Vinayakam SUbramaniam: A semiconductor company recently published a study showing how distributed package modelling improves the accuracy of on-chip power integrity analysis, leading to better chip-package co-design and co-simulation. We also see the increasing impact of dynamic voltage drop on timing, leading to clock jitter issues on-chip. Another trend we see is that more people are moving to design-dependent power grids.


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