Xilinx Inc. recently announced the Vivado Design Suite. It enables an IP and system centric next-generation design environment. Especially meant for the next decade of ‘All-Programmable’ devices, it is said to accelerate the integration and implementation up to 4X.
Neeraj Varma, director-sales, India, Xilinx, discusses the need for having an integrated design environment with Pradeep Chakraborty, elaborating on the productivity benefit and value add of the Vivado Design Suite. Excerpts:
August 2012: Elaborate on the need for an integrated design environment. How is the Vivado Design Suite addressing it?
When building systems, designers are encountering a new set of integration and implementation design-productivity bottlenecks. On the integration level, they consist of integrating algorithmic C and register-transfer level (RTL) IP; mixing DSP, embedded processor, connectivity, logic and mixed-signal domains; verifying blocks and ‘systems’; and design re-use.
The implementation bottlenecks include hierarchical chip planning and partitioning; multi-domain and multi-die physical optimisation; multi-variant design vs. timing closure; and late ECOs and the rippling effects of design changes.
To address the integration and implementation bottlenecks and allow users to take full benefit of the system integration capabilities of these All Programmable Devices, Xilinx created the powerful Vivado Design Suite.
Vivado tools allow designers to be extremely efficient and productive as they leverage a new generation of All Programmable devices, not only for programmable logic but for programmable systems integration, in automotive, consumer, industrial control, wired and wireless communications, medical and many other applications.
More specifically, when creating next-generation designs, engineers can use the Vivado tools to overcome numerous productivity bottlenecks in integration and implementation, as listed above.
What exactly is the definition of programmable system integration? How will it help designers?
Xilinx’s All Programmable technologies enable flexible, scalable embedded designs, achieving increased system performance and accelerated design productivity.
Among the main benefits of Vivado Design Suite, we have enabled in Vivado an IP packager that uses the IP-XACT standard to package up IP and used AutoESL in Vivado HLS. This IP can be imported into our IP catalogue, like Xilinx IP. This enables the IP to be shared across a company or it can even be encrypted using IEE1735p technology and shared between companies. In addition, IP can be placed and routed for re-use, reducing the effort of the end user. Examples of IP that could be packaged up are:
* full uP/DSP systems,
* C/C++/SystemC designs generated via Vivado HLS,
* System IP that collates multiple smaller IPs together using our IP integrator tool, and
* Any other blocks designed by the user.
What is the productivity benefit and value add of the Xilinx Vivado Design Suite?
The Vivado Deign Suite has been built from the ground up. All of the tools are being re-written to improve the usability and performance. Additionally, all the tools share a common database which enables cross-probing between the different views and enables early estimation of key design parameters. This has been made possible by the complete re-write of all the tools. The adoption of industry standards has further facilitated quicker integration and implementation of designs comprising IP from various sources.
Overall, Xilinx has seen the Vivado Design Suite accelerate both the integration and implementation phases of a design by up to 4x based on various field-tested design runs by Alliance Program Members, customers, and our own teams.
Xilinx has also used AutoESL to develop Vivado HLS, a high level synthesis tool, which allows the designers to:
* Simulate the algorithms and perform algorithmic exploration at the C level. This is many thousands of times quicker than HDL simulation.
* Insert pipelining and parallelism without having to modify any C code.
* Go from C to HDL quickly. This allows the user to explore several different FPGA implementations of the algorithm with different levels of pipelining and parallelism. Vivado HLS will summarise throughput, logic size and power. This allows the user quickly see if system requirements are met.
* Package up IP using the IP-XACT standard and add standard interfaces like AXI. This facilitates integration into the Vivado IDE allowing algorithmic IP to be integrated quickly into full designs and be re-used.
This makes the conversion from C, C++ or SystemC descriptions to working hardware far quicker and less prone to errors than the more traditional manual conversion.
What are the trends in terms of the adoption of programmable systems and growth?
Xilinx is one of only a handful of semiconductor companies with the resources, commitment and business model to justify an ‘all-in’ investment strategy with each new generation of advanced chip-making technology.
Our business is driven by several long-term global trends in the electronics industry, such as:
* Insatiable intelligent bandwidth demand, as wireless and wire-line traffic surges to accommodate everyone, everywhere.
* Broadening markets, as millions of new consumers demand low cost access to modern conveniences.
* Relentless system integration, as designers put more functionality onto ever fewer chips.