Effect of shrinking geometries
Modern integrated circuit (IC) process technologies offer higher-density packaging as a natural consequence of reduced device sizes, making the optimal use of power-down modes increasingly important. This also reduces the stress-handling capacity of the device, however. For instance, a 28nm device has a thinner gate oxide than its 180nm technology counterpart. Thus, the stress applied by the gate voltage in power-cut mode would be more likely to rupture the smaller device. In addition, layout dependent parameters could also cause catastrophic failures in smaller-geometry devices.
All of these effects make power-down modes increasingly desirable for modern devices. Packed with features, the modern chip comprises of millions of devices, each of which can contribute to the leakage current when kept on. Optimising feature usage and powering down unused parts of the chip can save a major portion of this leakage. Make sure that the vendor supports these modes explicitly though, rather than trying to develop your own power-down capability.
A few more situations
The power-down puzzle has more pieces. What if we cut the ground connection as well, since that opens another low-impedance path? This is similar to an electrostatic discharge (ESD) situation where I/O pins are forced directly without enabling supplies, and if the signal strength is sufficient, it might trigger the electrostatic discharge (ESD) protection structure, causing high currents to flow through other connected I/O pins and creating a false power-up situation. A more probable case is a signal that is somewhat weaker, but still powerful enough to reach the supplies through a path, such as the I/O clamp. The signal may not be able to trigger the supply clamp, but could create unexpected ghost voltages on the supplies, which could cause unknown states of operation depending on the topology of the chip. In either case, if the situation persists, the chip might be damaged, unless the previous stage has already stopped supplying high current. If the signal strength is not sufficient to trigger the I/O clamp, it still might stress the first transistor it encounters, possibly damaging it after prolonged operation.
How about disconnecting the supplies and pulling the supply inputs low? Now the chip has no floating supplies and no chance of triggering any ESD structure, but the p-type metal-oxide semiconductor (PMOS) drain can reach a higher voltage than the body, forward-biasing the drain-to-body diode. The current from the preceding stage would then flow through the PMOS device to ground until the device burns out, the previous stage gives up or the designer notices the alarm.
Power-down for complex systems
Power-down modes result in a faster, safer system-wide response, making them an indispensable feature, especially when looking at the full signal chain in complex systems. Complete power cut-off could be considered if interactions between components are limited, or the system as a whole is simple enough to ensure no complications occur.
The author is a CAD engineer at Analog Devices Inc and works predominantly in AMS verification, behavioural modelling, and ESD protection for AMS designs.