As SRAM scaling slows, a new embedded memory adds more on-chip memory and reduces dependence on external DRAM and HBM for AI chips.
As conventional SRAM struggles to shrink beyond the 5nm process node, Israeli-Swiss startup RAAAM Memory Technologies has developed GCRAM, a CMOS-compatible embedded memory designed to increase on-chip memory density and reduce dependence on external DRAM and high-bandwidth memory (HBM). Rather than replacing SRAM entirely, the company says GCRAM is intended to complement it by targeting larger on-chip memory blocks where its density and power advantages are most effective.
“For decades, SRAM scaled with every new process node, but from around 5nm onwards that scaling has almost stopped,” said Dr. Robert Giterman, CEO of RAAAM. “This has created a memory bottleneck because chips can no longer increase on-chip memory capacity at the same pace as logic.”
According to the company, the slowdown in SRAM scaling has become a growing challenge for AI accelerators, networking processors and other high-performance chips. As memory occupies a larger share of the die, designers increasingly rely on external DRAM or HBM, leading to higher power consumption and greater memory access latency.
“We are not planning to replace the entire memory stack that is currently implemented with SRAM,” Robert said. “GCRAM targets those SRAM use cases that can benefit from smaller size and lower power consumption, while smaller SRAM instances and processor caches can continue to use SRAM.”
Instead, the company sees GCRAM being deployed in large embedded memory arrays used in AI accelerators, networking devices and other compute-intensive processors. In these applications, chip designers can either fit more on-chip memory within the same die area or reduce die size while maintaining the existing memory capacity, lowering manufacturing costs and reducing traffic to external memory.
Unlike many alternative embedded memory technologies that require additional fabrication steps or special process modules, GCRAM is built entirely with standard CMOS devices. The technology stores data dynamically and therefore requires periodic refresh, which the company manages through a dedicated refresh controller supplied with the memory IP.
RAAAM also does not view SRAM vendors as direct competitors. Instead, it expects GCRAM to become another layer in the memory hierarchy, sitting between conventional on-chip SRAM and off-chip DRAM or HBM. The company believes this approach can help chip designers ease the growing memory bottleneck without replacing established memory technologies that remain better suited for smaller caches and latency-critical applications.
