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Location: Noida
Company: STMicroelectronics
Drive to “zero-defect”. Responsibilities encompass the development of a verification test bench, the development of verification components, test case development for simulation, debugging failures and creating simulation cases for various studies. As an experienced professional, work with the cutting-edge verification methodologies on standalone IPs, Subsystem level and SoC level.
Responsibilities
- Verification planning, reviewing, architecture definition, Verification test bench development and implementation
- Development of verification test bench components such as drivers, monitors, response checkers as well as use most advanced UVM VIPs.
- Development of direct and constrained-random stimulus, Understanding and analysis of RTL code, functional, assertion coverage results.
- Strong skills in debug, failure re-creation and root cause analysis
- Gate level simulations (unit delay, and with SDF annotated) and its debugging
- Test pattern debugging and testing for verification and automatic testers
- Continuous improvement of verification methods/tools/flows/processes together with EDA partners. Finding cost-effective and innovative verification techniques
- Assertion-based verification and automated testcase/scenario generation (eg. Perspec) will be a plus
Technical background/Key Skills
- Qualification: Bachelors/Masters in Electronics/Computer Science
- VHDL/Verilog, System Verilog, C language
- OVM/UVM, class-based verification methodologies
- Deep Understanding of ARM multicore-based SoC architecture
- AMBA – AXI, AHB, APB bus protocols
- NIC/FlexNOC interconnect architecture knowledge
- In-depth knowledge or ARM-based core. Understanding of Trace and Debug infrastructure.
- Knowledge of memory controller and NVM will be a plus
- Scripting proficiency – PERL, Python, UNIX/LINUX
- Simulation tools like – Xcelium/VCS/Questasim. Perspec. Planning and regression tools like VManager
- Exposure to any of defect and version management tool
