Tuesday, April 23, 2024

Kansas Lava to Simulate Circuits

The code is listed below:

 [stextbox id=”grey”]

import Language.KansasLava
import Language.KansasLava.Fabric
import Language.KansasLava.VHDL

halfAdd :: Signal i Bool -> Signal i
Bool -> (Signal i Bool, Signal i Bool)
halfAdd a b = (carry, sum)
where carry = a `and2` b
sum = a `xor2` b

fabric :: Fabric ()
fabric = do
i0 i1 let (c,s) = halfAdd i0 i1
outStdLogic “carry” c
outStdLogic “sum” s

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main = do
k writeVhdlCircuit “halfAdd” “halfAdd.
vhd” k
mkTestbench “halfAdd” “.” k

The above code can be compiled and run using:

$ ghc –make halfAdd.hs

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$ ./halfAdd


Following files are created in the directory where halfAdd is executed: halfAdd.vhd, halfAdd_tb.vhd and halfAdd.do. halfAdd.vhd contains the VHDL implementation of the circuit, halfAdd_tb.vhd contains testbench VHDL and halfAdd.do contains a ModelSim script to run the test bench.

halfAdd.vhd file is listed below:

 [stextbox id=”grey”]library IEEE;
use work.lava.all;
use work.all;
entity halfAdd is
port(clk : in std_logic;
i0 : in std_logic;
i1 : in std_logic;
carry : out std_logic;
sum : out std_logic);
end entity halfAdd;
architecture str of halfAdd is
signal sig_6_o0 : std_logic;
signal sig_7_o0 : std_logic;
signal sig_2_o0 : std_logic;
signal sig_3_o0 : std_logic;
signal sig_5_o0 : std_logic;
signal sig_4_o0 : std_logic;
sig_6_o0 <= sig_7_o0;
sig_7_o0 <= (sig_4_o0 xor sig_5_o0);
sig_2_o0 <= sig_3_o0;
sig_3_o0 <= (sig_4_o0 and sig_5_o0);
sig_5_o0 <= i1;
sig_4_o0 <= i0;
carry <= sig_2_o0;
sum <= sig_6_o0;
end architecture str; [/stextbox]

halfAdd_tb.vhd file is listed below:

 [stextbox id=”grey”]

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
entity halfAdd_tb is
end entity halfAdd_tb;
architecture sim of halfAdd_tb is
signal clk :
std_logic := ‘1’;
signal rst : std_logic := ‘0’;
constant input_size : integer := 16;
constant output_size : integer := 16;
signal input : std_logic_vector(3 downto 0):= (others => ‘0’);
signal output : std_logic_vector(3
downto 0);
runtest: process is
FILE halfAdd_input : TEXT open read_
mode IS “halfAdd.in.tbf”;
FILE halfAdd_output : TEXT open write_
mode IS “halfAdd.out.tbf”;
VARIABLE line_in,line_out : LINE;
variable input_var : std_logic_vector(3
downto 0);
variable output_var : std_logic_
vector(3 downto 0);
variable needs_rst : boolean := false;
while not endfile (halfAdd_input) loop
READLINE(halfAdd_input, line_in);
clk <= ‘1’;
wait for 5 ns;
input <= input_var;
if needs_rst then
rst <= ‘1’;
end if;
output(3 downto 2) <= input_var(3
downto 2);
wait for 20 ns;
clk <= ‘0’;
wait for 20 ns;
if needs_rst then
rst <= ‘0’;
needs_rst := false;
end if; output_var := output;
WRITE(line_out, output_var);
WRITELINE(halfAdd_output, line_out);
wait for 5 ns;
end loop;
end process;
dut: entity work.halfAdd
port map (
clk => clk,
i1 => input(2),
i0 => input(3),
sum => output(0),
carry => output(1)

end architecture sim;


halfAdd.do file is listed below:

 [stextbox id=”grey”]vlib mywork
vcom -work mywork Lava.vhd
if [catch {vcom -work mywork halfAdd.
vhd} einfo] {
puts $einfo
} else {
vcom -work mywork halfAdd_tb.vhd
vsim -lib mywork halfAdd_tb
add wave -r /*
run -all

Download source code: click here

Shakthi Kannan is MS in information technology from Rochester Institute of Technology, Rochester, New York, USA. Currently, he is working as senior R&D engineer at Manufacturing System Insights, Chennai. He is a software enthusiast who blogs at shakthimaan.com


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