A new AI chip architecture combines in-memory and analogue computing techniques to reduce power consumption, potentially enabling advanced AI applications beyond traditional data centres.
Researchers at Princeton University have developed a new AI chip architecture designed to run advanced artificial intelligence workloads while consuming significantly less power than conventional AI hardware. The project aims to make powerful AI systems practical in smaller devices and energy-constrained environments.
The architecture combines multiple computing approaches, including in-memory computing and analogue processing, to reduce the energy and time typically spent moving data between memory and processors. According to the research team, the design addresses key challenges affecting the scalability and efficiency of current AI systems.
Unlike many existing AI accelerators that are largely confined to data centres due to their power requirements, the proposed architecture is intended for deployment across a broader range of environments. Researchers say it could support advanced AI capabilities in edge devices, autonomous systems and other applications without relying on large, power-hungry computing infrastructure.
By reducing energy consumption while maintaining performance, the design could help expand the adoption of AI in applications where power availability is limited. The researchers believe the approach may enable more efficient deployment of AI technologies outside traditional computing facilities.
The project has received support from the US Defense Advanced Research Projects Agency (DARPA), which awarded $18.6 million to further develop and evaluate the technology. The funding will support efforts to advance the research and translate the architecture into practical AI hardware.
Researchers say the work represents a step toward energy-efficient AI computing platforms capable of supporting future generations of intelligent applications while reducing dependence on large-scale computing systems.
