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Location: Bengaluru
Company: Onsemi
As a Physical Verification Engineer, you will play a leading role in the physical design domain for developing Onsemi’s cutting-edge image sensor products. You will work on the physical verification (PV) flow and chip closure activities. You need to work closely with the cross-functional teams like physical/Analog design, PDK, IP, ESD and Packaging teams, in chip closure and tape-out activities.
Experience/Requirements
- BSEE required, MSEE preferred with 2-3 years of experience in physical verification.
- Expertise with industry-standard CAD tools (preferably Calibre) with a strong emphasis in physical verification and tape-out.
- Hands-on experience in layout and schematic entry using Cadence Virtuoso with a good understanding in semiconductor device physics, models and technology scaling.
- Strong DRC/LVS debug experience
- Self-motivated, excellent communication and interpersonal skills.
- Programming skills in TCL/Perl/Skill will be a plus.
Responsibilities
In this role, you will be responsible for the physical desig,n specifically on physical verification and chip signoff. Some specific tasks include:
- DRC/LVS
- Antenna/ERC
- DFM/DFY
- Debugging and resolving DRC/LVS/ERC/DFM/DFY errors.
Qualifications
BSEE required, MSEE preferred with 2-3 years of experience in physical verification.
