APPLY HERE
Location: Bengaluru
Company: NVIDIA
What you’ll be doing
- As a member in our team, you will be responsible for the design and implementation of state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression.
- Your responsibility will also include verification and silicon bringup of Scan ATPG and other DFT features.
- In addition, you will help develop and deploy DFT methodologies for our next generation products.
- Be apart of innovation to strive improve the quality of DFT methods.
- You will also need to work with multi-functional teams to incorporate DFT features into the chip.
- Occasional travel and also some late hours online meetings involved during critical milestones.
What we need to see
- BSEE or MSEE from reputed institutions or equivalent experience with 2+ years of experience
- You should be well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design.
- Experience in RTL and Gates verification and simulation.
- You need to be familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500.
- Strong DFT knowledge in Scan ATPG, compression techniques and memory test.
- Strong analytical and problem solving skills with good scripting knowledge (either Perl / Python)
