In the world of electronics goods, where margins are razor thin, manufacturers try to keep product cost low to maintain a competitive edge. In a bid to achieve this, they tend to constrain designers to achieve the desired function by using lowest-cost PCBs and circuit components. Using electromagnetic compatibility (EMC) design techniques for PCBs and selecting components with high levels of EMC is a luxury, they think, they cannot afford.
Most are of the opinion that problems can be fixed using additional EMC suppression components (aptly called electromagnetic interference or EMI fixes) at the end of the product development cycle, if at all it is found that these are really required. Following this approach, it is not immediately obvious that the cost of these last-minute fixes will in fact be many times the cost of EMC measures incorporated during PCB design in the initial stages of the product development cycle. So the approach of lowest bill of material cost will actually result in considerable increase in product cost.
In order to design a PCB with low emission and susceptibility, two aspects have to be kept in mind. First, the ground (or signal return) system and second the PCB layout. For any PCB it is desirable to have a low-impedance ground system that is effective in draining out EMI currents, but it is the PCB layout that is the single-most-effective factor in designing a good PCB; a good layout not only reduces ground track impedance but also avoids common impedance coupling.
High speed PCB design: Digital circuit layout and noise
Digital ICs incorporating logic gates are often a source of impulsive transients due to finite charge recovery times of transistors. Whenever a logic gate changes state, a short pulse of current is drawn from power supply rails because both the totem-pole transistors at the output momentarily conduct. Now the inductance of ground tracks opposes this sudden change producing a back electromagnetic force, which shows up as a spike. This spike is referred to as ground bounce or shoot-through.
In order to reduce this generated transient, all such circuits must be designed with a low-inductance ground system. Also, a source of charge should be provided near each logic gate, which ensures that the high transient current is not drawn all the way from the Vcc.
The ground track impedance can be reduced by reducing the value of track inductance, reducing the loop area enclosed by the current spike and by reducing the length of the tracks over which this current flows by providing a source of charge near each logic gate.
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Hi Asif, you can read this article from our magazine Electronics For You.