In an exclusive interview, Seema Johar of Compcarta speaks with EFY’s Akanksha Sondhi Gaur about why setting up an EDA environment can be harder than designing a chip, and how her team is simplifying the process through an integrated, browser-based platform.
Seema Johar, Co-Founder and Product Director, Compcarta Solutions Pvt Ltd
Q. Why was Compcarta founded? What gap does it fill, and what does its name mean?
A. Compcarta was incorporated in 2019 and is headquartered in Greater Noida. The team spent its initial years developing the technology before entering the market, focusing on delivering mature, practical solutions rather than making early announcements. The name was chosen to be simple, memorable, and closely associated with computers. The company was founded to address long-standing gaps in the electronic design automation (EDA) industry identified through the founders’ academic and professional experience. Recognising that existing VLSI design tools are often expensive, difficult to access, and complex to use, the team set out to develop an EDA platform that is more accessible, cost-effective, and user-friendly for startups, design companies, innovators, and educational institutions.
Q. How would you define the company’s core innovation in one sentence?
A. Our core innovation is enabling the entire chip design flow, from schematic capture to GDSII, in a single web browser window, bringing the complete EDA workflow together on one integrated platform.
Q. How does your end-to-end EDA architecture overcome infrastructure and accessibility challenges?
A. We are building an end-to-end EDA ecosystem that goes beyond software tools to provide the complete chip design infrastructure, including toolchains, compute resources, licensing, maintenance, upgrades, and technical support through cloud or on-premises deployment. This enables startups and design companies to focus on chip innovation rather than infrastructure management. The platform combines open source EDA tools with proprietary technologies to improve usability, performance, and industry readiness while filling technology gaps with in-house solutions. Its portfolio includes CircuitPro for analogue and digital schematic design, EDA Cloud for browser-based RTL-to-GDSII implementation without software installation, and Quick CDC, a proprietary clock domain crossing analysis tool that automatically resolves around 70–80% of common violations. Additional in-house tools under development include ATPG, formal verification, logic equivalence checking (LEC), and analogue layout. The design flow spans the entire semiconductor development process—from schematic or RTL design, verification, linting, and CDC analysis through Igniter and Quick CDC, to synthesis using integrated or customer-supplied PDKs, followed by physical implementation on Catalyser for floorplanning, placement, clock tree synthesis, routing, and GDSII generation. By integrating the complete RTL-to-GDSII workflow on a single platform, the company aims to complement established EDA vendors while making professional chip design more accessible and affordable for startups, innovators, and growing semiconductor companies.
Q. Which parts of the platform are open source, and where does your proprietary IP add value?
A. We combine open source EDA engines with proprietary technologies rather than using open source tools unchanged. Its front-end verification framework is proprietary, while the underlying compilation and simulation engines are open source. Quick CDC has been developed entirely in-house, and the synthesis flow uses an open source engine enhanced with proprietary optimisations to improve netlist quality. The same approach extends to physical implementation, where open source tools are augmented with in-house innovations to enhance performance and usability. The ecosystem also supports interoperability, allowing designers to move design files into compatible third-party tools for specific stages, such as placement, and seamlessly re-import them into the workflow. In addition, the company has developed proprietary analogue and digital schematic design tools and is building fully in-house solutions for analogue layout, automatic test pattern generation (ATPG), logic equivalence checking (LEC), and formal verification.
Q. How is your platform developed and what role do industry and academia play in its evolution?
A. All the core development is done in-house. Our team has strong expertise in CDC analysis and other areas of chip design, so we solve the engineering challenges internally. We do seek guidance from experienced industry mentors, but their role is purely advisory, while the actual design and development remain within our team. Although we do not have formal partnerships or MoUs with industry or academic institutions, we actively collaborate through feedback and technical discussions. IIT Delhi, one of our customers, regularly shares feedback that helps us understand real-world design challenges and refine our solutions. We also engage with semiconductor startups and domain experts facing EDA access challenges, and their inputs help us identify gaps and continuously improve our platform and tools.
Q. What key technologies has Compcarta developed in-house, including its proprietary CDC analysis?
A. A major engineering challenge was clock domain crossing (CDC) analysis. During development of the complete RTL-to-GDSII flow, the team found that unresolved CDC violations could prevent tape-out, prompting it to build a proprietary CDC analysis engine instead of relying on existing solutions. Leveraging the founders’ expertise, the tool was developed entirely in-house and has become one of the company’s key technical innovations. Another major innovation is EDA Cloud, a fully in-house, browser-based platform that integrates the complete chip design workflow, from schematic capture and RTL development to CDC analysis, synthesis, and physical implementation, within a single interface. By managing the underlying compute infrastructure and EDA toolchain, the platform enables engineers to run compute-intensive tasks such as synthesis, placement, and routing without requiring high-end local hardware or complex IT setup, allowing them to focus on chip design rather than infrastructure management.
Q. What technological breakthroughs enabled platforms like CircuitPro and EDA Cloud?
A. The biggest breakthrough was taking open source EDA tools and making them industry-ready. While they offer strong functionality, they cannot simply be connected into a complete commercial chip design flow, so we aligned them with industry workflows, identified the gaps, and built our own technologies wherever needed. That led to the development of our Quick CDC analysis engine and CircuitPro for analogue and digital schematic design, both built from scratch. Another breakthrough was EDA Cloud, which brings the entire RTL-to-GDSII flow onto a single web browser. Designers can use a pre-integrated technology or bring their own PDK, run the complete flow with just a few clicks and inspect, modify, or rerun any stage of the design. This significantly reduces design iteration time while keeping the workflow seamless, and it has received encouraging feedback from startups and academic users.
Q. What was the biggest challenge in integrating multiple EDA tools into a unified platform?
A. The biggest challenge was not simply integrating multiple EDA tools but making them work together as a seamless, production-ready system. We wanted users to do much more than run the RTL-to-GDSII flow through a graphical interface. Within the same browser window, they can also access a Linux terminal to inspect directories, scripts, logs, reports, and other files while a design is running, so making the tools, infrastructure, and user interface work together in real time requires significant engineering effort. We also had to maintain responsiveness while integrating compute-intensive tasks such as synthesis, placement, routing, and layout visualisation into a browser-based platform. Users can move between different stages of the flow, view layouts, and interact with the design environment without leaving the browser. Achieving that level of integration, speed, and usability required extensive in-house engineering and became one of the defining innovations behind EDA Cloud.
Q. Can you walk us through Catalyzer’s RTL-to-GDSII implementation flow?
A. Catalyzer delivers a nine-stage RTL-to-GDSII flow covering linting, Quick CDC, synthesis, STA, floorplanning, placement, CTS, routing, and GDSII generation, with script-level control through an integrated Linux terminal. It supports Sky130, GF180, and Nangate45 PDKs, with ASAP7 and ISB130 under evaluation, alongside customer-specific PDK integration, including support for GlobalFoundries customer PDKs. While direct QoR and runtime comparisons with commercial EDA tools are limited by the lack of public benchmarks, the platform is priced at just 10–20% of conventional solutions, making it 70–80% more affordable. Its browser-based workflow has also earned positive feedback from IIT Delhi for its ease of use, cloud accessibility, and suitability for academia and startups.
Q. What proprietary optimisations have you introduced to improve PPA, runtime, and design convergence?
A. Improving power, performance, and area (PPA) is an ongoing area of development for us. We have already introduced optimisations during the synthesis stage, and our flow scripts are designed to produce well-optimised results out of the box. At the same time, we continue to improve the underlying tools themselves by modifying and enhancing their internal implementations wherever required, rather than treating them as fixed components. Our focus is on steadily improving optimisation quality, runtime, and overall design convergence as the platform evolves.
Q. Which technology nodes, PDKs, and foundry environments does Catalyzer support?
A. We have not yet completed a chip tape-out using our own flow, as we are still in the early stages and are working closely with design teams to validate the platform. Our current flow supports the Sky130 and GF180 open source PDKs, and we are collaborating with customers and foundries to validate additional integrations. Since we are an EDA company, tape-outs are carried out by design companies using our platform rather than by us directly. The underlying open source tools and PDKs integrated into our platform have already been widely validated, with published literature reporting their use in more than 600 tape-outs globally. We are also seeing increasing adoption of these open source EDA flows in Europe, and our platform is designed to support foundry-specific PDK integration, allowing customers to bring their own PDKs as required.
Q. How do you ensure sign-off quality and tape-out readiness?
A. Achieving full tape-out readiness requires close collaboration with design teams, so that is where we are currently focusing our validation efforts. Internally, however, we have been extensively testing the flow using industry-standard designs. We have successfully closed designs of up to one million gate counts using the integrated open source PDKs, and the results have been very promising. These results have also been reviewed positively by industry and academic experts. As part of our validation process, we have run more than 50 design trials across a range of industry-relevant designs, including RISC-V processors and Network-on-Chip (NoC) architectures. We conduct these trials for every major tool we develop to evaluate design quality, timing, and overall flow robustness before deploying them to customers.
Q. How does CircuitPro Analog deliver browser-based analogue design with desktop-class performance?
A. CircuitPro Analog evolved from Slide CircuitPro, a PowerPoint-integrated schematic design tool with patent applications in India and the US, and CircuitPro Digital. Designed to simplify analogue design, it offers a browser-based workflow with pre-built component libraries, support for Sky130, GF180, and customer-specific PDKs, along with process corner and transistor model selection. The platform automatically generates SPICE netlists and testbenches, supports DC, AC, and transient simulations, and includes built-in electrical rule checks (ERCs) to detect violations before simulation—a capability missing in many open source analogue design tools. It also streamlines complex design tasks and accelerates simulation and waveform generation, delivering a desktop-like EDA experience through a web browser.
Q. What additional capabilities make CircuitPro Analog suitable for professional analogue design?
A. Direct comparisons of quality of results (QoR), runtime, and design quality with commercial EDA tools are difficult because benchmark data from established vendors is generally not publicly available. The semiconductor EDA ecosystem is relatively closed, making objective comparisons challenging. Where we can make a clear comparison is on cost. Our platform is priced at approximately 10 to 20 per cent of conventional commercial EDA tools, making it 70 to 80 per cent more affordable. Usability is harder to quantify, but the feedback has been highly encouraging. IIT Delhi used our cloud-based platform for a semester-long course and subsequently endorsed its ease of use, browser-based accessibility, and infrastructure, noting that it is well suited for academia, startups, and design teams while demonstrating the potential of an indigenous Indian EDA ecosystem.
Q. What sets you apart from commercial and open source EDA platforms?
A. Compcarta bridges the gap between expensive commercial EDA platforms and fragmented open source tools by delivering a cloud-based, browser-native ecosystem built on accessibility, usability, affordability, and scalability. The platform manages the complete EDA toolchain, enabling startups, design companies, service providers, and educational institutions to focus on chip design without investing in complex IT infrastructure. Priced at just 10–20% of conventional commercial EDA solutions, it offers 70–80% lower costs while integrating the strengths of both commercial and open source ecosystems. Although direct QoR and runtime comparisons are difficult due to the lack of public benchmarks, IIT Delhi independently found the platform to be 95% comparable to the EDA tools it already used in terms of quality, usability, and accessibility, and later adopted it for a semester-long course. Cloud computing underpins the platform’s scalability, supporting everyone from individual designers to large organisations without requiring high-end local hardware. Looking ahead, the company is embedding AI directly into its EDA tools to enhance productivity, optimise design quality, and improve engineering decision-making throughout the chip design process.
Q. Could you share your business traction and key adoption mileston es so far?
A. We are a bootstrapped, completely indigenous company, so we’ve consciously kept the team lean and focused on quality rather than numbers. Resources haven’t been a major challenge, and we continue to bring in interns, with around 20 working with us at the moment, giving us a good balance between expanding the team and staying focused on product development. On the technology side, we’re addressing gaps in the EDA ecosystem by developing tools for areas such as equivalence checking and analogue layout while expanding foundry integration. We already support open source PDKs including Sky130, GF180, and Nangate45, with ASAP7 and ISB130 being added, and we’re working with foundries to bring more PDKs into our flow. That process takes time, but we’re moving in the right direction. Overall, the current momentum in India’s semiconductor ecosystem and the policy support around it are creating a favourable environment for companies like ours to grow.
Q. Which markets are adopting your tool, and how will cloud and AI support its scale and growth?
A. Compcarta has focused on maturing its technology before scaling commercially. A key milestone came in April 2026, when its complete EDA suite was onboarded to the National EDA Tool Grid, serving over 300 institutions and nearly 100 startups. Within two months, the platform had been adopted by 50+ institutions and seven DLI companies, while IIT Delhi also used it for a full-semester course. The company is expanding engagements with additional startups and academic institutions. Tool validation combines industry-standard benchmarks, design trials, and expert reviews. Where public benchmarks exist, such as for ATPG, the platform meets established QoR metrics; elsewhere, results are assessed through industry and academic evaluations. While not targeting parity with commercial tools at advanced nodes, the platform is delivering strong results for the bulk process nodes widely used by Indian product companies. Over the next five years, the company plans to embed AI to improve design quality and productivity while expanding its portfolio with LEC, formal verification, analogue layout, and SoC design tools, to make professional chip design more intelligent, affordable, and accessible.
Q. Why should a chip design engineer choose Compcarta?
A. The biggest value we offer is that engineers can focus entirely on designing chips instead of worrying about the EDA toolchain. We take care of the infrastructure, tool integration, workflows, and the complexities of making different tools work together, so they can concentrate on innovation rather than building and maintaining the design environment. Our platform is also highly cost-effective, supports open source PDKs, and works closely with foundries to simplify the path to tape-out. In short, we remove the engineering overhead so designers can build better chips, faster and at a much lower cost.
Q. What message would you like to share with India’s semiconductor industry?
A. Chip design is inherently complex, and as India accelerates its semiconductor ambitions, building indigenous EDA capabilities is just as important as investing in manufacturing and chip design. Without a strong domestic EDA ecosystem, the industry will continue to rely on expensive external technologies. We have talented students, researchers, and entrepreneurs, but many still lack access to the right tools, infrastructure, and industry exposure. Enabling them is essential to building a self-reliant semiconductor ecosystem. That is the vision driving Compcarta. We see ourselves as an enabler aligned with India’s Semiconductor Mission, making professional chip design more accessible while strengthening the country’s long-term EDA ecosystem.
