Tuesday, May 28, 2024

Harnessing The SHAKTI For Microcontroller Chips

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“As an academic institution, we’ve done everything we can to develop the Shakti microprocessor, and now I need you to make it accessible to the world” — Prof. Kamakoti Veezhinathan.

It was a momentous occasion when IIT Madras announced the release of the Shakti microprocessor in 2018. While the adoption of this chip across strategic sectors, such as defence, nuclear power installations, government agencies and departments, is yet to be seen on a massive scale, startups such as Mindgrove Technologies are working towards making it accessible to the world.

Founded and incubated under IIT Madras in 2021 by co-founders and former colleagues, Shashwath TR (CEO) and Sharan Srinivas J (CTO), fabless semiconductor startup Mindgrove Technologies harnesses the potential of open source technology and the RISC-V Instruction Set Architecture (ISA) to create a high-performance microcontroller chip operating on a 28-nanometre technology node with a SHAKTI core.

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The Shakti processor’s open source nature, released under a permissive BSD three-clause license, eliminates licensing fees and sales royalties typically associated with buying proprietary chips, reducing costs. “The RISC-V ISA combines lessons from legacy ISAs like x86, ARM, MIPS, and more, resulting in impressive performance efficiency for resources invested. The chip’s microarchitecture is designed to be simple, minimising area and power consumption, thus reducing production costs linked to chip size. We benefit from financial and infrastructure support and mentorship provided by IIT Madras, helping us identify and address potential issues early on,” says Shashwath.

The choice of a 28-nanometre technology node, however unconventional, allows the company designing chips for machine learning and characterisation-focused signal processing and vision, to deliver the required performance without resorting to excessive complexity or gate counts, resulting in power efficiency. “Our primary emphasis is on optimising performance, and then we progressively eliminate components and features until we achieve the desired power consumption. We aim to create a chip perfectly suited for its intended purpose, effectively a ‘right-sized’ chip for the task at hand,” Sharan explains.


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