A ‘JedAI’ For Development Of AI

By Jay Soni

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Joint Enterprise Data and AI (JedAI) Platform is an EDA software that can optimize multiple runs of multiple engines across an entire SoC design and verification flow.

Credit : Cadence

“As chip design size and complexity have increased exponentially over the past decade, the volume of design and verification data has also increased with it,” said Dr. Venkat Thanvantri, VP of AI R&D at Cadence. And based on current state-of-the-art technology the development silicon chip and their architecture doesn’t seem to go far as it should. We see that once a chip design project is completed, the valuable data is deleted to make way for the next project.

The Cadence Joint Enterprise Data and AI (JedAI) Platform enables a generational shift from single-run, single-engine algorithms in electronic design automation (EDA) to algorithms that leverage big data and artificial intelligence (AI) to optimize multiple runs of multiple engines across an entire SoC design and verification flow. It enables engineers to glean actionable intelligence from massive volumes of chip design and verification data, opening the door to a new generation of AI-driven design and verification tools that dramatically improve productivity and power, performance, and area (PPA).

JedAI enables engineers with following features:
  • Design data such as waveforms and coverage in functional verification, physical layout shapes, timing/power/voltage/variation analysis reports, design RTL, netlist and SDC specifications in design implementation
  • Workload data such as runtime, memory usage, and disk space usage, as well as metadata about the inputs to each job and dependencies between them,
  • Workflow data, such as the tools and methodology used to create a design,
  • Highly scalable: enterprise-grade scalability and security, enabling design optimization across multiple runs, tools, users, designs, and EDA domains.
  • Actionable intelligence: Quickly compares metrics across different versions of the same design and/or multiple designs, providing recommended actions to improve PPA and increase verification coverage.
  • Workflow management technology: The integrated workflow management capability allows users to efficiently capture chip design methodologies and automatically transfer design data between projects through data connectors.
  • Customized analytics: Offers open industry-standard user interfaces such as Python, Jupyter Notebook, and REST APIs, enabling designers to create custom analytics applications.

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