META-DX2+ enables secure ethernet PHY family with port aggregation for enterprise and cloud interconnect.
The increased demand for bandwidth and security in the network infrastructure driven by growth in hybrid work and geographical distribution of networks is re-defining borderless networking. Led by AI/ML applications, the total port bandwidth for 400G (gigabits per second) and 800G is forecasted to grow at an annual rate of over 50%, according to 650 Group. This dramatic growth is expanding the transition to 112G PAM4 connectivity beyond just cloud data center and telecom service provider switches and routers to enterprise ethernet switching platforms.
Microchip Technology Inc. has introduced META-DX2+ Ethernet PHY portfolio to integrate 1.6T(terabits per second) of line-rate end-to-end encryption. It also integrates port aggregation to maintain the most compact footprint in the transition to 112G PAM4 connectivity for enterprise ethernet switches, security appliances, cloud interconnect routers and optical transport systems.
META-DX2+’s configurable 1.6T datapath architecture is 2x in total gearbox capacity and hitless 2:1 protection switch mux modes enabled by its unique ShiftIO capability. The devices include IEEE 1588 Class C/D Precision Time Protocol (PTP) support for accurate nanosecond timestamping required for 5G and enterprise business critical services. Microchip enables developers to expand their designs to add MACsec and IPsec based on a common board design and Software Development Kit (SDK).
- Dual 800 GbE, quad 400 GbE and 16x 100/50/25/10/1 GbE MAC/PHY
- Integrated 1.6T MACsec/IPsec engines that offload encryption from packet processors so systems can more easily scale up to higher bandwidths with end-to-end security
- Greater than 20% board savings compared to competing solutions that require two devices to deliver the same 1.6T gearbox and hitless 2:1 mux modes
- XpandIO enables port aggregation of low-rate Ethernet clients over higher speed
- Ethernet interfaces, optimized for enterprise platforms
- ShiftIO feature combined with a highly configurable integrated crosspoint enables flexible connectivity between external switches, processors, and optics
- Device variants with 48 or 32 Long Reach (LR) capable 112G PAM4 SerDes including programmability to optimize power vs. performance
- Support for Ethernet, OTN, Fibre Channel and proprietary data rates for AI/ML applications