“Firmware- And Hardware- Based Mechanisms Protect Data From Sudden Power Loss Events”

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Engineers can check a solid-state drive’s (SSD’s) health condition using self-monitoring analysis and reporting technology (SMART) tool. If the SSD or data get corrupted, they can try to recover the data. C.S. Ma, chief technical officer, Phison Electronics Corp., discusses the technologies, encryption techniques, protocols and data protection mechanisms for SSDs with Deepshikha Shukla.


C.S. Ma chief technical officer, Phison Electronics Corp
C.S. Ma chief technical officer, Phison Electronics Corp

Q. How is eMMC better than HDD?

A. NAND storage (including SSD, eMMC, UFS, SD and USB) has the benefits of lower power consumption, stronger vibration resistance due to zero moving parts, lighter weight and smaller form factor, than such traditional storage devices as HDD.

eMMC is faster than HDD in both sequential and random performance, especially with less power consumption, and is much stronger against vibration.

Q. How does NVMe technology enable extremely fast operation in SSDs?

A. Unlike AHCI, traditional storage (for example, HDD) protocol, NVMe (NVM Express) is defined and optimised specifically for non-volatile memories, such as NAND flash, which means NAND controller can utilise not only PCIe interface but NVMe protocol for extreme SSD performance.

Further, NVMe protocol allows issuing multiple commands to the SSD at the same time. This lets the SSD process more than one command to boost performance. In addition, adoption of direct memory access largely reduces latency and command overhead, while introducing out-of-order processing improves performance.

Q. How does PCIe help analyse an SSD’s performance?

A. PCIe has defined higher bandwidth and a more effective way of data access to allow NAND controller to optimise data handling flow from host to memory units.

Key benefits of PCIe specification have been implemented to NAND controller IC design to deliver the best user experiences.

Q. How is data protection achieved in case of power failure?

A. In firmware-based mechanism, it is done to minimise data buffer/cache size while keeping performance at a certain level. In addition, firmware adds some management information to user data to minimise data loss during the next power-on data-recovering process.

In hardware-based mechanism, it is usually implemented for SSD by adding capacitors on PCB assembly design as a power backup. So, when sudden power loss happens, capacitors provide sufficient power to the SSD to flush buffer/cache data to NAND flash.

Both firmware- and hardware-based mechanisms protect data from sudden power loss events.

Q. How do you ensure that data is protected throughout the life of an SSD?

A. From the data integrity point of view, controllers and firmware have mechanisms to ensure data integrity throughout the life of the SSD (such as ECC engine, E2EDPP, etc).
Firmware has two mechanisms to check data integrity: dynamic check and static check.

Dynamic check means when host is reading data, firmware will check if error bit has reached the set threshold and refresh data accordingly.

While, static check means firmware will scan original data in the background to check data damage caused by instability of memory cells and refresh data whenever necessary.

Q. How can sequential reads and writes be optimised in memory design?

A. NAND controller IC design and NAND storage solution providers have multiple ways of optimising performance (sequential and random), including application-oriented algorithm (such as video surveillance and phone app operation) and some patented firmware mechanism that could improve NAND storage performance (for SSD, UFS, eMMC, SD or USB).

Also, the controller has implemented hardware mechanism that could accelerate some data retrieval to improve performance. Moreover, higher storage capacities with more memory units could dramatically improve performance by higher rank of data read/write parallelism.

Q. What are the multiple layers of safety to protect data integrity?

A. A series of advanced data protection mechanisms, such as BCH, strong ECC, LDPC, E2EDPP (end-to-end data path protection) and RAID, prevent data corruption due to instability of NAND flash cells.

Additional information resulting from user data is added and stored into memory units. The same information is used to compare and recover data if unexpected data corruption occurs.

Further, NAND flash controller implements error detection and correction mechanism to ensure data and corresponding control signals are well-protected, so that data integrity is guaranteed all the way from host to memory units.

Q. How is hardware-based encryption achieved in SSDs?

A. Controller ICs have a hardware accelerator designed to utilise multiple hardware-based encryption layers, without sacrificing performance.

For encryption type, PHISON controllers have implemented AES self-encrypted and OPAL 2.0 mechanisms, which are optimised by the hardware accelerator to balance encryption and performance.


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