JOB: India-DFT Engineer At NextSilicon In Bengaluru

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Location: Bengaluru

Company: NextSilicon

NextSilicon is looking for a talented and experienced DFT engineer to play a crucial role in the DFT implementation of the company’s next SOC. A Design for Test (DFT) Engineer plays a critical role in the semiconductor and electronics industries, focusing on developing and implementing testing methodologies to ensure the functionality, reliability, and manufacturability of integrated circuits (ICs) and other hardware designs. The primary goal of a DFT Engineer is to integrate test structures within the design of electronic components to facilitate efficient testing throughout the lifecycle of the product, from production to deployment and maintenance.

Requirements

• 4 to 10 years of experience in DFT methodology and implementation is a must
• Strong understanding of digital design and test principles.
• Proficiency in DFT techniques, such as Scan compression, SSN, Scan Stitching, fault models (stuck-at, delay tests, IDDQ, Small Delay, etc), IEEE P1500, MBIST, IEEE 1149.1/6 (Boundary scan), IEEE 1687, etc.
• Experience with EDA tools (e.g., Synopsys FusionCompiler, TestMax, Mentor Tessent) and scripting languages (e.g., Python, TCL, Makefile, etc).
• Knowledge of IC design flows, verification tools, SDC, fault models.
• Ability to identify, analyse, and resolve testing challenges.
• Work effectively within multidisciplinary teams, communicating complex technical details clearly.
• Proven success in development of complex custom ASIC products in advanced process nodes.
• Hands-on experienced and successful taped out several ASICs.
• Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals.

Responsibilities

• Define DFT Architecture and Methodologies for the next-generation SoCs.
• Perform scan, MBIST, Boundary scan insertion and ensure architectural spec is met.
• Develop high-quality tests to verify DFT functionality in RTL and gate-level (no-timing and timing) simulations.
• Analyse fault models and optimise for high coverage (stuck-at, transition, path delay, IDDQ, etc).
• Working closely with cross-functional teams to develop and verify DFT’s structures and constraints.
• Work closely with Test Engineering for test program development and silicon bring-up, diagnosis, Yield improvement, etc.