Can AI help engineers design chips faster? A new set of tools can create RTL code, check designs, estimate power and performance, and reduce development time.
Rapidus Corporation has announced a suite of AI-based design tools aimed at supporting semiconductor development for its 2nm manufacturing platform. The tools will roll out under the company’s Rapid and Unified Manufacturing Service (RUMS) framework. The first releases include Raads Generator and Raads Predictor.
The tools are intended for semiconductor design engineers, ASIC developers, SoC architects, RTL designers, and chip design teams working on advanced-node semiconductor products. They can be used to automate RTL creation, analyze and optimize designs, estimate power, performance, and area (PPA), identify design issues, and accelerate the path from specification to manufacturing.
Raads Generator is an electronic design automation (EDA) tool built on large language model technology. It enables engineers to enter semiconductor specifications and automatically generate register-transfer level (RTL) design data optimized for Rapidus’ 2nm process technology. This can help reduce manual coding effort and speed up early-stage chip design.
Raads Predictor is designed for RTL debugging and optimization. It can quickly estimate power, performance, and area (PPA), allowing engineers to evaluate design trade-offs, identify potential bottlenecks, and refine architectures before moving further into the design flow.
According to the company, using the two tools together can reduce design time by up to 50% and lower design costs by up to 30%.
The additional AI-driven tools include Raads Navigator/Indicator, which uses large language models to assist with quality assurance, design reviews, and engineering support; Raads Manager, a layout design tool that applies machine learning and AI to generate hierarchical design configurations and streamline physical design workflows; and Raads Optimizer, which uses machine learning and AI to identify parameters that improve power, performance, and area metrics.
Together, the tools are designed to support multiple stages of semiconductor development, including RTL generation, verification, debugging, quality assurance, floorplanning, layout design, and design optimization for advanced logic chips.
