AI tools automate specification-to-RTL and RTL-to-HLS workflows, aiming to increase chip design productivity and support architectural exploration.
Rise Design Automation has launched two AI-assisted platforms, IPCreate and IPTransform, for semiconductor design. Unveiled at DAC 2026, the platforms automate parts of the flow between design specifications, high-level synthesis (HLS), and RTL. The company claims the flow can enable a single engineer to produce about one million gates per week.
IPCreate is designed to take a written specification or a MathWorks model and generate C++, SystemC, or SystemVerilog models. These models are then synthesised to produce technology-optimised RTL. The platform is aimed at reducing the engineering effort involved in translating design specifications into hardware implementations.
IPTransform takes the opposite approach. It starts with existing RTL and a testbench and uses AI reasoning on the elaborated design to compare the implementation with the specification. It then generates an HLS model and a corresponding specification. This can provide a higher-level representation of an existing design for simulation and architectural exploration.
The flow uses HLS as an intermediate layer between the specification and RTL. Rise says its HLS models can simulate about 30 times faster than equivalent RTL models. This can allow designers to evaluate designs and architectural changes at a higher level without relying entirely on RTL simulation or emulation.
The company says the HLS approach also addresses some of the limitations of directly using general-purpose large language models for hardware generation. An LLM can produce code that is not synthesizable or can contain errors. IPCreate is designed with checks intended to keep generated models synthesizable and verifiable.
Rise says its HLS flow has also addressed quality-of-results and timing issues that have historically limited the use of HLS-generated designs in downstream synthesis.
The platforms support MathWorks models, C++, SystemC, and SystemVerilog as inputs. IPTransform can also be used with legacy RTL where the original specification or design intent may no longer be readily available. The resulting higher-level model can be used as a source of truth for system-level modelling and architectural exploration.
