UCIe support lets adaptive SoCs connect with chiplets for AI, RF, communications, and other applications.
AMD is adding Universal Chiplet Interconnect Express (UCIe) 1.1 support to its Versal adaptive SoCs, allowing them to connect with specialised chiplets within the same package. The move gives system designers a way to combine adaptive SoCs with additional AI, RF, processing, security, or communications silicon without putting every function into a single chip.
The Versal RF Series will be the first Versal devices to support UCIe 1.1. The devices will offer up to four independent UCIe-SP (standard-package) interfaces and up to two UCIe-AP (advanced-package) interfaces, providing several terabits per second of aggregate in-package bandwidth.
UCIe is an open standard for communication between chiplets. Instead of connecting separate silicon components through board-level interfaces, designers can place multiple chiplets in the same package and use UCIe to transfer data between them.
With the new connectivity, designers can pair Versal devices with commercial or custom chiplets for functions such as AI acceleration, RF processing, specialised computing, security, communications, and co-packaged optics. Possible combinations include RF analog front ends and data converters, AI accelerators, CPUs, GPUs, security engines, communications processors, and application-specific ASICs.
The approach can also make it easier to change individual functions in a system. Rather than redesigning an entire SoC when a particular function needs to be added or modified, designers can potentially use a different chiplet while retaining the rest of the design.
The Versal RF Series already combines RF data converters, dedicated DSP hardware, AI Engines, and programmable logic in a single adaptive SoC. AMD says the devices provide up to 80 TOPS of heterogeneous DSP computing. UCIe extends this architecture by allowing additional specialised silicon to be connected within the package.
Moving connections from the circuit board into the package can shorten the distance that data needs to travel between components. This can help reduce latency and interconnect power while supporting higher bandwidth, depending on the system implementation.
For applications such as RF, AI, networking, and communications, the chiplet approach allows designers to decide which functions should remain in the adaptive SoC and which should be implemented using dedicated silicon. It can also allow existing chiplets and silicon blocks to be reused across different designs.
