A new optical interconnect design combines 7.2TB/s bandwidth, integrated light sources, and direct-drive signalling to reduce power, latency, and component count in AI computing systems.
Huawei has introduced the Hi-ONE optical engine, an NPO (Near-Packaged Optics) solution designed for high-bandwidth interconnects in AI computing systems. The optical engine provides a total transmission capacity of 7.2TB/s and integrates the light source within the optical engine, targeting higher interconnect density while reducing system-level power and latency.
The Hi-ONE has already been deployed in the Ascend 960 SuperPoD, which uses a “UnifiedBus plus Hi-ONE” architecture. According to the company, this implementation reduces the number of 800G optical modules by 48,000, helping lower power consumption and the number of discrete components in the system. Fewer optical modules can also simplify the interconnect architecture and improve overall system reliability.
The key features are:
- 36 integrated optical transceiver channels
- Compound, silicon-photonic, and optoelectronic RF chips
- Approximately 66% lower power consumption
- About 90% reduction in transmission latency
- Designed for long-duration AI training workloads
At the optical-engine level, Hi-ONE integrates 36 optical transceiver channels into a single unit. Its architecture combines compound optical chips, silicon photonic chips, and optoelectronic RF chips, with optical, electrical, mechanical, thermal, and magnetic elements designed as a unified system.
A key feature is its built-in light-source architecture, which eliminates the need to rely on a separate light-source arrangement. This enables a more compact optical interconnect implementation while supporting high-density data transmission. Huawei states that the integrated approach can improve overall reliability by up to 10 times, which is particularly relevant to AI workloads involving prolonged training and continuous data movement.
For power and latency reduction, Hi-ONE uses a linear direct-drive architecture that removes the requirement for high-power optical DSP chips. The company claims this approach cuts power consumption by approximately 66% and reduces transmission latency by about 90% compared with conventional implementations.
The technology is aimed primarily at AI data centres, high-performance computing systems, accelerator clusters, and high-bandwidth chip-to-chip or system-level interconnects, where increasing compute density is placing greater demands on optical connectivity.
The development also aligns with broader industry efforts to standardise NPO technology. In May 2026, an OIF proposal for a 12.8TB/s NPO module, submitted by the China Academy of Information and Communications Technology, Huawei, and other companies, entered the standardisation process with support from more than 40 industry vendors.
