AnalogAI is using silicon-proven memBrain SAGE IP to build sub-one-watt edge AI processors that can train and adapt models directly in real-world environments.
AnalogAI is developing its first real-world edge AI processors around Silicon Storage Technology’s (SST) memBrain Synaptic Analog Generative Engine (SAGE) IP, targeting a key limitation in edge AI: devices that can adapt their models while operating rather than relying solely on pre-trained inference. The processors combine analog compute-in-memory (aCIM) with proprietary hardware-aware algorithms to support training and inference on the same device. The approach is aimed at applications such as humanoid robots, drones, and vehicles, where environmental conditions can change rapidly and sending data to the cloud for retraining can introduce latency, connectivity dependence, and additional power consumption.
A major advantage is the targeted sub-one-watt power envelope. SST’s memBrain architecture performs computation close to where AI model data is stored, reducing data movement between memory and processing elements a significant contributor to energy consumption in conventional AI architectures. At the heart of the IP is the memBrain Tensor In-Memory Logic Element (TILE). It uses an ESF3-based bitcell capable of storing up to 8 bits per cell at nanoamp-level power, alongside custom memory arrays, decoders, driver circuits, and low-power bitcell control. The architecture also integrates optimised DACs and ADCs, summation circuitry, high-voltage bias circuits, and proprietary test circuitry to support analog neural-network computation.
The underlying memory technology is SST’s SuperFlash, providing non-volatile storage with data retention and endurance characteristics suited to embedded applications. This allows AI parameters to remain on-chip rather than depending on external memory. The memBrain SAGE IP has already been developed and deployed using 40nm and 28nm processes, giving AnalogAI a silicon-proven foundation rather than starting the compute-in-memory design from scratch. SST is also developing a 22nm roadmap, potentially enabling further improvements in power efficiency and compute density.
For AnalogAI, the significance lies in combining aCIM hardware with algorithms designed around the characteristics of the silicon. This co-optimisation could allow edge processors to respond to changing surroundings locally, particularly in systems where low latency and energy efficiency are more important than running increasingly large AI models.
