An AI-powered design tool converts specifications into optimised chip logic, refines existing designs, and evaluates power, performance, and area to help engineers accelerate semiconductor development and verification.
Cadence ChipStack AI Super Agent’s RTL Generation Agent automates register-transfer-level (RTL) code generation and optimisation, helping semiconductor engineers develop functionally accurate digital designs while improving power, performance, and area (PPA).The new agent uses natural-language prompts and established electronic design automation (EDA) technologies to translate high-level specifications into production-ready RTL.
In early evaluations, the tool achieved an average 24% reduction in area and 18% reduction in power compared with code generated using foundation models alone. The generated RTL was reported to be 100% functionally accurate in these evaluations. These results indicate how combining AI with established design and verification engines can help engineers produce more efficient chip implementations than relying on AI-generated code alone.
The RTL Generation Agent extends the existing ChipStack AI Super Agent beyond automated verification and debugging into logic creation and refinement. Engineers can describe the required functionality in natural language, allowing the agent to generate RTL and analyse its implementation against PPA objectives. By bringing optimisation into the early design stages, the workflow can help identify inefficiencies before they become more expensive to address later in development.
The key features are:
- Multi-agent orchestration: Coordinates specialised AI agents across chip-design workflows.
- EDA tool integration: Connects AI workflows with established electronic design automation tools.
- Implementation and signoff correlation: Links design automation with implementation and signoff engines.
- Cross-domain AI portfolio: Complements the wider ChipStack, InnoStack, and ViraStack platforms.
- Early-access deployment: Expanded capabilities are planned for selected customers in Q4 2026.
The system also supports modifications to existing RTL. Engineers can specify changes to functionality, architecture, or PPA targets at a high level, and the agent can update the code while analysing and verifying its functionality and performance. This capability is particularly useful when adapting legacy designs to new requirements, potentially reducing the manual effort involved in repeated design revisions.
These chips must meet demanding power and cost constraints while supporting safety-critical automotive functions. The automated workflow is intended to improve productivity from specification development through RTL implementation, an important consideration as software-defined vehicles and autonomous-driving systems increase semiconductor complexity.
The agent follows an architecture in which a supervisory AI system coordinates specialised agents that use established EDA software. This approach aims to maintain consistency between AI-generated design changes and the underlying implementation and signoff processes. The expanded capabilities are expected to become available to select early-access customers in the fourth quarter of 2026. The development reflects a broader move towards agentic AI systems that coordinate multiple engineering tasks rather than simply generate code, potentially helping design teams manage increasingly complex semiconductor projects.
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