Tuesday, April 23, 2024

Yosys: Your Solution for Verilog RTL Synthesis

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So, you are working on your circuit design and your Verilog code is ready! You have tried your hand at simulation and the code is functioning correctly. What next? Synthesis is the answer. Yosys is a framework for Verilog RTL synthesis. It is an open source tool for performing logical synthesis. Falling under Internet Software Consortium (ISC) licence category, it is a free software that takes in your Verilog/Very high speed integrated circuit Hardware Description Language (VHDL) code and gives out a gate-level netlist that your printed circuit board (PCB) designing software understands.


Fig. 1: View of an RTL netlist
Fig. 1: View of an RTL netlist

How it helps

With presence on Reddit, Stack Overflow and GitHub (github.com/cliffordwolf/yosys), the tool can run on Ubuntu, Fedora and Windows operating systems (OSes). Here are a few features that would keep you thinking about the experience, long after you have finished working on your design.

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With most synthesis tools being proprietary, Yosys is one tool you can easily download and start working with your code anytime you want. To work with Yosys, you will just need a C++ compiler with C++11 support and a few tools like GNU Flex, GNU Bison and GNU Make.

Yosys reads your Verilog code, supporting Verilog 2005 version, converts it into its internal format, elaborates the design to establish design hierarchy, performs optimisations and converts the code into a netlist.

Standard algorithms. There are a variety of algorithms, called passes, to perform register transfer level (RTL) behavioural and logic synthesis of your code. These are modelled to suit different applications, and you can modify these to suit your requirements using synthesis scripts.

A synthesis script is simply a file with commands that will be executed in sequence on the file being read by the tool. The table (next page) shows a basic synthesis script that can be used to synthesise most designs. You can even add additional passes to existing ones by extending Yosys C++ code base. This is further made easy by making sure all passes use the same interface, so as to ease the effort from the user to understand or modify the source code. Yosys even supports multi-bit values and multi-port memories.

Flexibility. You can choose to generate three kinds of netlists, namely, a simple RTL netlist that describes the circuit in terms of registers and data transfer, a complementary metal oxide semiconductor (CMOS) gate-level netlist that converts a circuit to its basic form characterised by CMOS gates and a coarse-grain netlist that reduces the design to an implementation of coarse-grain cells. The netlist you obtain is simply decided by which technology library you map the design to.

Visualise how your design looks. With the tool, you can view this netlist in a gate-level representation, that is, a diagram consisting of the circuit design in terms of basic logic gates. In effect, cells that represent the corresponding function replace all operators and logic. When command show is used for a netlist, it invokes an open source software for graph visualisation called as Graphviz. This then converts the netlist into a pictorial representation for the user to observe the design.

verilog rtl
Fig. 2: CMOS gate-level netlist

4CB_box_2Interactive navigation. To analyse and investigate designs, it is often required to not just view circuit diagrams but also narrow down and scrutinise their interesting parts. Yosys allows you to change the appearance of the circuit diagram and save it in the name and format you wish. Instead of waiting for the synthesis process to complete, you can simply add command Shell at the point you want to check in the design. Synthesis is stopped at that point for you to interact with the design. Yosys also allows you to perform different types of synthesis on different sections of the code at one go.

Exchange between formats. When you talk about parsing designs and exchanging sequential logic between programs, formats like Berkeley Logic Interchange Format (BLIF) and bit-precise word-level format or BTOR come to the fore. All you need are simple commands that convert your Verilog design into these formats, and vice-versa.

More than just synthesise. Not just synthesis, Yosys lets you perform advanced analysis and circuit transformations. You can extract finite state machines and perform operations on these. It also offers minimum support to frequent sub-circuit mining and technology mapping by finding sub-circuit isomorphism.

Latest additions. Yosys 0.5 sports a log file even for warnings obtained while synthesising your code so as to make sure your design can be re-worked to perfection. Flip-flops with an enable signal promise to be a boon for digital circuit design. Commands for equivalence checking, block random access memory (BRAM) support, enhanced commands, drivers and performance improvements add a spark to Yosys.

Mapping to the technology library

One of the main aim of synthesis is to map your design to a particular technology library. To understand why this step is necessary, imagine you are drawing a circuit layout. The first thing you would need is the size or the fit-to-scale factor. In other words, the technology library provides the basic unit in the design of the layout. Yosys has an inbuilt technology library consisting of basic CMOS cells.



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