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Development and support of ASIC tech files and development of ASIC flows/methodologies. Enabling APR tools for placement/routing and Timing to support new process node. physical designs (RTL to GDSII) of test vehicles to evaluate developed tech file and APR flow/methodology. Regular Interaction with Stakeholders including vendors during techfile and flow development. Timely tracking of issues and resolving customer support issues. Write good documents for ASIC flows and PDK. Train the users and design engineers on ASIC flows and tech file usage. Debug the complex design issues and help the design and CAD teams in PDK and flow deployments.
BTech/BE/MTech/ME/MSc in Electronics/Computer science with Industry experience in ASIC PDK kit/Physical design/ ASIC Design automation role.Hands-on experience with Synopsys and Cadence Place and Route tools, Timing tools, Floor planning, IR Drop and Physical verification. Should have good understanding of Verilog/VHDL. Exposure to low power techniques and PPA analysis. Knowledge of tcl and perl scripting is a must. Strong presentation and communication skills within an international environment. Team oriented in parallel to ability to work independently and bring new initiatives. Good in stakeholder management and should be detailed oriented.