Tuesday, June 18, 2024

ASIC Physical Design Engineer At Synopsys In Bengaluru

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Location: Bengaluru

Company: Synopsys

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

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Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. 

ASIC Physical Desing Engineer

We’re looking for ASIC Physical Design Engineer to join our team.
Does this sound like a good role for you?

In this role, you will work on development of robust ASIC design flow to build & verify our standard cell libraries  to achieve the best PPA with all aspects of quality.  Work involves Place and Route using  ICC/ICC-II/Fusion Compiler.

Key Qualifications

  • Bachelors or Masters degree in electronics or electrical engineering  or equivalent from reputed universities with 2-3 year experience in ASIC design or internship of few months
  • Working experience on advance technology nodes like 28nm,16nm,14nm,10nm, 7nm   with different foundries
  • Clear understanding of CMOS & ASIC flow in submicron process nodes
  • Knowledge on  Place & route , physical verification (DRC/LVS) & Timing analysis skills
  • Be familiar with all stages in the ASIC design flow including Synthesis, DFT , timing analysis, floor planning, power planning, CTS, ECO flow, STA, power analysis
  • Be familiar with the Low power concepts & UPF/CPF format
  • Good understanding about Tech file, liberty, lef, def, gds & standard cells view generation process (Milkyway & NDM)
  • Experience using Synopsys (ICC/ICC-II/Fusion Compiler ,DC,PT) tools ,Cadence (soce/innovus, RC/genus) design tools.


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