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Master’s/Bachelor’s Degree in Electrical/Electronics engineering with 1-3 years of experience in Analog Mixed Signal Layout. Successful candidate would be responsible for layout in advanced CMOS technologies including floorplan, placement, routing, DRC, LVS etc. Additionally, you would be responsible for doing automation for layout needs including writing scripts to improve layout productivity. You should have worked on FinFet technology (7nm or below would be advantage) on various analog mixed signal blocks such as PLL, Bandgap, ADC, DAC, SERDES, IO etc. Engineer should be well versed with tools such as Virtuoso/XL/GXL, Calibre etc. You are required to work with circuit designers to meet design specifications. This job requires excellent teamwork, good communication and strong problem solving skill.
- Responsible for independent planning and execution of layout for various designs in 7nm technology nodes and below
- Hands on experience in all stages of the design such as Floor planning, Placement, Layout, Physical Verification etc.
- Must have Perl, TCL, C-Shell and Skill scripting skills to help out the centralized layout team
- Sound understanding of ESD and Latch up concepts
- Experience with Cadence Virtuoso-XL and Mentor Graphics Physical Verification Tools is a must
- Must be experienced in at least one of the industry standard version control tools such as Cliosoft, DesignSync or I.C. Manage etc.
- Strong debug capabilities with parasitic extraction, LVS/DRC and other Physical verification checks
- Strong problem solving skills
- Sound knowledge of device matching, pitch matching, double patterning, Electromigration /IR drop and other Layout Dependent Effects
- Excellent verbal and written communication skills