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Performs logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs. Participates in the development of Architecture and Microarchitecture specifications for the Logic components. Provides IP integration support to SoC customers and represents RTL team.
Knowledge of Verilog system Verilog, DC., ICC, and PrimetimeUnderstand of tradeoff and design optimization technique between performance power and area general scripting and programming skills (Python, Perl, C/C++)Formal verification experience would be plus