Monday, April 22, 2024

JOB: Turing Design Verification Staff Engineer At Qualcomm In Noida

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APPLY HERE

Location: Noida

Company: Qualcomm

General Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what’s possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

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Minimum Qualifications

Bachelor’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

OR

Master’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Required to work on IP / Subsystem level verification and own various DV tasks from Test plan creation, coverage model development, test case writing and coverage closure.

Skills: UVM, SV, SVA (assertions)

Expected to do full triage’ing in collaboration with design team and proactively report status of progress

Should be proficient in System-Verilog and scripting language like Shell, Perl . Must have RTL/gate level simulation debug experience. Should have a working knowledge of bus protocols like AHB/AXI . candidates should have 5-8 years experience.

very sharp in debugging

good in SV, UVM, Assertions, GLS

Able to join ASAP (in less than 2 weeks)

Should be proficient in System-Verilog and scripting language like Shell, Perl . Must have RTL/gate level simulation debug experience. Should have a working knowledge of bus protocols like AHB/AXI . candidates should have 5-8 years experience

  • Hands on knowledge/expeience in System verilog and UVM
  • Solid knowledge of C and Scipting language like python
  • Must have RTL and Gate level simulation debug experience
  • Working knowledge of bus protocol like AHB/AXI

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