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Locations: Bengaluru and Hyderabad
Company: NVIDIA
What You Will Be Doing
You will be responsible for the creation of “state of the art” UVM-based verification test benches and methodologies to verify complex IP’s and Sub-systems. You will also get to work on system-level verification using C/C++. During the course of a project you would end up driving the following aspects of verification for your unit:
- Architect the testbenches and craft a verification environment using UVM methodology
- Define test plans, tests and verification infrastructure for modules, clusters and system
- Build efficient and reusable bus functional models, monitors, checkers and scoreboards
- Implement functional coverage and own verification closure
- Work with architects, designers, FPGA and post-silicon teams to ensure that your unit is robust
What We Need To See
You should be BTech/MTech with 2+ years of experience in the verification closure of complex Unit, Sub-system or SOC level verification. If you have experience in at least a few of the following domains, we will have an excellent match for our needs:
- CPU verification, Memory controller verification, Interconnect verification
- High Speed IO verification (UFS/PCIE/XUSB)
- 10G/1G Ethernet MAC and Switch
- Bus protocols (AXI/APB)
- System functions like Safety, Security, Virtualisation and sensor processing
- Experience in the latest verification methodologies like UVM/VMM
- Exposure to industry-standard verification tools for simulation and debug is a requirement
- Exposure to Formal verification would be excellent
- Good debugging and analytical skills.
- Good interpersonal skills, ability to work as an excellent teammate with excellent communication skills to collaborate with cross-cultural teams and work in a matrix organisation
