HDL and FPGA: From Gates to Microprocessors

Anurag Nigam is adjunct faculty in electronics and telecommunications, Government College of Engineering, Aurangabad


Digital designs can be described precisely and concisely using hardware description languages (HDLs) like Verilog and VHDL. Both languages are capable of digital circuit modelling, design and verification but have unique sets of strengths and weaknesses.

Digital circuits find applications ranging from control systems through RADAR to communications. A vast range of application areas has been possible due to fast modelling and prototyping using HDLs and reconfigurable hardware like field-programmable gate arrays (FPGAs). FPGAs are a sea of configurable circuits or logic blocks (CLBs) embedded in a matrix of switches. CLBs consist of look-up tables, flip-flops and multiplexers, which can be connected to realise a digital operation. A number of CLBs can be networked together to form entire digital systems. One such digital system is a microprocessor.

Two microprocessor architectures are quite popular: Von Neumann and Harvard. Von Neumann architecture uses the same memory to store data and instructions, while Harvard architecture uses different memories for data and instructions. Nevertheless, both the architectures use two units, data path and control path. Data path operates on data, while control path operates on instructions and accordingly generates control signals to control data path.

This article focuses on design and implementation of microprocessor data path. Here we use Xilinx Artix 7 family of FPGAs and VHDL. For prototyping, numerous prototyping boards are available. We have used a Digilent Nexys 4 DDR board.

Data path

Data path operates on operands stored in internal data registers and stores the result in another data register. Fig. 1 shows data path under the control of control path. Control path issues control words to data path in proper sequence and at proper times in order to control the operation on data. Data path generates status signals, which may provide valuable feedback to control path.

Data path and control path
Fig. 1: Data path and control path

Data path shown in Fig. 1 has data input, control word input, status word output and data output. Width of data word is specified in bits. For our designs we have a generic that stores data width and can be altered globally.

Important components of data path include multiplexers, data bus, arithmetic and logic unit (ALU), barrel shifter, multiplier, register file, universal shift register and output buffers.

Digital circuits can be classified into combinational circuits, sequential circuits and state machines. Data path components are combinational and sequential circuits but not state machines. Combinational circuits do not have the sense of passing time simply because these do not have memory. Their outputs depend on the current values of inputs only.

Sequential circuits have the sense of passing time and time-based ordering of operations. These have memory. Their outputs depend on current and previous values of inputs and previous values of outputs. Sequential circuits have clock and all state changes are synchronised to clock edges. Multiplexer, data bus, ALU, multiplier and buffer are combinational circuits. Register file, barrel shifter and universal shift register are sequential circuits.

Data path architecture

Fig. 2 shows data path architecture. Control, status and address lines for various blocks are not shown. Data bus is a multibit interface to which drivers are connected through their output buffers. Inputs of various blocks can be directly interfaced to the data bus. Here the width of the data bus is a generic called ‘width.’

Data path architecture
Fig. 2: Data path architecture

Two multibit 2:1 multiplexers are used: One is used to select between Data In and the computed result from data path output, to be written into register file. The other is used to select one of the outputs from ALU and multiplier as data path output.

Register file is a set of local registers used by data path. There is one input and two output ports. The two outputs are the two input operands to the ALU or the multiplier. The input is used for writing to one of the registers. Write register is selected by the write address and two read registers are selected by the two read addresses.

One of the two operands passes through a barrel shifter. Barrel shifter shifts the bits by specified count to left or right. The new bits on the left or the right are 0s or rotate around of the word.

The two operands beyond barrel shifter are passed on to the ALU and the multiplier as inputs. The ALU is capable of one of the eight operations. The multiplier multiplies two operands and provides the multiplexed output.

The output of the second multiplexer moves to the output universal shifter. The universal shifter is capable of bit-wise left and right shift, serial-to-parallel conversion and multiplexing the output with a second input word. Output buffer at the output of data path provides an interface to the bus. This is required in case multiple data paths drive the output bus.

The various parts included in Fig. 2 are discussed along with VHDL codes in the following sections.



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