Tuesday, May 21, 2024

FPGA Prototyping Systems For Advanced SoC Design

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Integrated with NVIDIA technology and featuring new domain-specific applications, these platforms are set to redefine hardware debugging and software validation, accelerating time to market for industry leaders across various sectors.

Cadence Design Systems, Inc. has launched the new Cadence Palladium Z3 Emulation and Protium X3 FPGA Prototyping systems. This introduction marks an advancement from the previous Palladium Z2 and Protium X2 systems, addressing the growing complexity in system and semiconductor design, and accelerating the timeline for developing state-of-the-art System on Chips (SoCs).

The Palladium Z3 emulator incorporates a novel Cadence emulation processor which enhances compile speeds and provides extensive pre-silicon hardware debugging capabilities. The Protium X3 prototyping system is notable for its swift preparation times for pre-silicon software validation, even for designs that exceed a billion gates. Together, these systems enable a seamless workflow, using a unified compiler and shared interfaces, which facilitates quick design transition and testing from emulation to prototyping.

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SoC Testing with Enhanced Capacity and Advanced Integration

These third-generation systems deliver a capacity more than double that of their predecessors and a performance increase of 1.5 times, which significantly reduces design bring-up times and shortens the time to market. The scale of operations varies from 16 million gates to as large as 48 billion gates, allowing for comprehensive testing of large SoCs to ensure functionality and performance. 

Integrated with NVIDIA’s BlueField DPU and NVIDIA Quantum InfiniBand networking platforms, the Palladium Z3 and Protium X3 maintain continuity when shifting between virtual and physical interfaces. The systems also feature new domain-specific applications, including the industry’s first 4-State Emulation App, the Real Number Modeling App, and the Dynamic Power Analysis App, which support the management of increased system complexity and improve system-level accuracy. These platforms are critical for testing massive software before finalizing the chip design, becoming increasingly essential as SoCs grow in complexity. They are already being used by leading companies in AI, automotive, hyperscale, networking, and mobile chip sectors to achieve high throughput in hardware debugging and software validation.

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Akanksha Gaur
Akanksha Gaur
Akanksha Sondhi Gaur is a journalist at EFY. She has a German patent and brings a robust blend of 7 years of industrial & academic prowess to the table. Passionate about electronics, she has penned numerous research papers showcasing her expertise and keen insight.

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