A hardware TCP/IP stack enables ASIC and FPGA designs to handle 100 Gbps networking without a host processor.
CAST has introduced the TCPIP-100G Hardware Stack IP core, a hardware-based TCP/IP protocol stack for application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) designs. The core enables devices to transmit and receive data at speeds of up to 100 Gbps over Internet Protocol (IP) networks using the Transmission Control Protocol (TCP), without requiring a host processor.
The TCPIP-100G core handles the full TCP/IP stack in hardware, allowing an integrating system to exchange data without running software on a processor. Designers configure network parameters through control registers and then stream data through the core. The hardware manages TCP connection establishment, maintenance and closure, along with packet retransmission, flow control and congestion control. It can operate as either a TCP client or server.
The core supports up to 32,768 simultaneous TCP sessions, with the number of sessions configurable at synthesis time. This lets you configure the same IP for smaller network endpoints or systems that need more connections, including data-server applications. Its networking functions include IPv4, Address Resolution Protocol (ARP) with cache, Internet Control Message Protocol (ICMP) ping reply, Virtual Local Area Network (VLAN) tagging based on IEEE 802.1Q, checksum generation and validation, and Jumbo and Super Jumbo frame support.
The core provides two packet-processing modes. Cut-through mode passes payload data with low latency and uses less memory, while store-and-forward mode delivers packets only after they have been verified and placed in order. Runtime-programmable parameters include local Media Access Control (MAC) and IP addresses, port and address filters, retransmission settings, window sizes and Maximum Segment Size (MSS), allowing the configuration to be adjusted for different networking requirements.
The TCPIP-100G core is designed for ASIC and FPGA implementations and is available with licensing options. Deliverables include synthesizable Verilog register-transfer level (RTL) source code or a targeted FPGA netlist, an integration testbench, simulation and synthesis scripts, and user documentation. An optional Universal Verification Methodology (UVM)-based verification environment is also available.
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