A voltage-controlled MRAM-based Ising machine integrates 96,000 all-to-all connected spins, with sub-nanosecond updates, and tackles combinatorial optimisation problems including electronic design automation routing and layer assignment.
Researchers at Beihang University, working with Suzhou Inston Technology and Empyrean Technology, have developed a spintronic Ising machine using a CMOS-integrated magnetoresistive random-access memory (MRAM) chip. The system contains 96,000 magnetic spins arranged in an all-to-all connected architecture and can update individual spins in 0.3 to 1 nanosecond..
Ising machines are specialised computing systems designed to solve combinatorial optimisation problems. Instead of evaluating solutions sequentially like a conventional processor, they represent an optimisation problem using interacting spins. The system then evolves towards a low-energy state, with the resulting spin configuration representing a candidate solution. Such architectures have been explored using quantum, optical and electronic implementations.
The new system uses the voltage-controlled magnetic anisotropy (VCMA) effect in magnetic tunnel junctions. Applying a voltage changes the magnetic anisotropy and therefore the energy barrier associated with the magnetisation state. This allows the researchers to control the probability of switching a spin using voltage pulses. The paper reports tunable single-pulse switching probability from 0 to 100 per cent through pulse-width control.
This voltage-controlled approach is important because conventional current-driven magnetic switching requires current to pass through the magnetic device during a write operation. The researchers instead use voltage to control the magnetic state, enabling the low-current operation required for their probabilistic Ising architecture.
The resulting VC-MRAM chip contains 96,000 spins and provides all-to-all connectivity. In an Ising machine, this means that the interaction between spins can represent a densely connected optimisation problem without requiring the system to reproduce those connections through a large number of external operations. The paper identifies this architecture as a way to implement an on-chip all-to-all Ising machine at large scale.
The reported spin-update speed is 0.3 to 1 ns, while the energy efficiency is below 40 femtojoules (fJ) per spin update. On Max-cut benchmark problems, the researchers report a system energy efficiency of 1.92 × 10⁵ solutions per second per watt. These measurements describe the demonstrated Ising architecture rather than the performance of a general-purpose processor across arbitrary workloads.
The researchers also moved beyond standard optimisation benchmarks by applying the hardware to electronic design automation (EDA). They demonstrated global routing and layer assignment problems, two tasks involved in determining how connections are arranged in an integrated circuit. Global routing determines paths for connections across a chip, while layer assignment determines which routing layers are used.
For the hardware demonstration, the VC-MRAM chip was mounted on a custom printed circuit board and connected to a Xilinx PYNQ-Z2 FPGA board. A host PC was used to map the optimisation problem to an Ising model and configure the required parameters. The FPGA then drove the VC-MRAM chip through iterative Ising computations, with the resulting spin states returned to the host system for analysis.
The architecture is therefore not a standalone commercial accelerator or a replacement for conventional EDA software. Instead, it demonstrates how a specialised magnetic computing device can be integrated into an optimisation workflow. The use of EDA problems is significant because it gives the researchers a practical workload in which a large number of possible configurations must be explored.
The work also demonstrates the difference between specialised optimisation hardware and conventional computing. An Ising machine does not provide the flexibility of a CPU or GPU for general-purpose workloads. Its advantage comes from mapping a particular optimisation problem onto physical spin dynamics and allowing the hardware to search for low-energy configurations. This makes the architecture more relevant to selected optimisation workloads than to general computing.
The researchers fabricated the VC-MRAM chip and evaluated its operation as a physical device rather than relying solely on simulation. The paper describes the system as a CMOS-integrated spintronic Ising machine and reports measurements from the fabricated hardware. It also provides source data through a GitHub repository, while the computer code and problem instances are available from the corresponding author on request.
For chip-design workflows, the demonstrated global-routing and layer-assignment applications provide a direct example of where such hardware could eventually be used. However, the reported results remain a research demonstration. Integrating an Ising accelerator into production EDA flows would require further evaluation of programmability, software integration, manufacturing scalability, reliability, workload coverage and performance against established optimisation methods.
The work shows how MRAM can be used for more than conventional non-volatile memory. By exploiting the stochastic switching behaviour of magnetic tunnel junctions and controlling it through voltage, the researchers have used the memory technology as the physical substrate for optimisation. With 96,000 interconnected spins and sub-nanosecond updates demonstrated on fabricated hardware, the result points towards specialised CMOS-integrated architectures for solving selected optimisation problems with lower energy consumption.
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