A new memristor chip expands associative memory capacity while cutting device count, recall time and energy use for low-power edge AI applications in intelligent devices.
Researchers at the University of Hong Kong (HKU) have developed a memristor chip that expands the capacity of brain-inspired associative memory while reducing hardware requirements for low-power AI systems.
Associative memory allows information to be retrieved from incomplete cues, similar to how the brain can recognise a person from a glimpse of a face or recall a song from a few notes. Conventional implementations are limited by network size, with larger memory capacity requiring more devices and increasing the risk of confusion between stored patterns.
The HKU team, led by Professor Can Li and PhD candidate Chengping He, combined a hardware-adaptive learning algorithm with a multilayer network architecture to overcome this limitation. The algorithm accounts for individual device imperfections during training rather than treating variations in real memristor hardware as errors.
Experimental results showed that the system could handle both binary and continuous-valued data while using up to 95% fewer devices. The chip also achieved roughly twice the storage capacity of a previous state-of-the-art design. For structured real-world data, its capacity increased faster than the network size, demonstrating what the researchers describe as superlinear scaling.
The integrated design exploits the parallel operation of the memristor crossbar. By updating the network simultaneously, the chip reduced recall time by up to 99.7% and improved energy efficiency by up to 8.8 times compared with conventional approaches.
These results were demonstrated on a fully integrated chip built around 64 × 64 memristor arrays, rather than through simulation alone. The architecture could support memory-centric AI applications where computing resources and energy are constrained.
The researchers see potential for intelligent edge devices, including sensors and wearables operating away from data centres. The work could help make neuromorphic hardware more practical by combining high-capacity associative memory with lower device counts, faster recall and improved energy efficiency.
