Wednesday, July 17, 2024

RISC-V Based Architecture Integrates Complex Memory Tasks to Processor

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Processor Akurra, modifies the standard RISC-V architecture and instruction set to support their memory allocation technology.

VyperCore, a UK-based startup located in Bristol, has achieved a significant milestone in the development of a new chip architecture that incorporates RISC-V. They have successfully demonstrated the RTL (Register-Transfer Level) design of this technology in a RISC-V processor simulation, executing code for the first time. They plan to release a hardware version of this technology by June 2024.

The technology will improve efficiency by transferring complex memory-related tasks, such as Garbage Collection, from software to the silicon layer. This integration into the processor itself reduces the overhead of running these tasks in the background, allowing the CPU to focus more on running the user’s application. During research, 7x acceleration in applications was observed.

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VyperCore’s first supported processor architecture is RISC-V. Their first processor, named Akurra, modifies the standard RISC-V architecture and instruction set to support their memory allocation technology. The processor’s RTL is currently operational in simulation, with its compiler supporting the extended instruction set. The runtime now delegates the garbage collection functionality to the silicon layer.

Their product development involves modifying an established processor architecture to embed their technology, updating the compiler to support the modified processor, and altering the language’s runtime software to shift memory allocation tasks to the silicon. This integrative approach was successful earlier in January when they ran standard Python code on the simulated core.

Looking forward, VyperCore aims to have the next version of the processor running on actual hardware, not just in simulation, by June. This development will enable their commercial partners to validate that their production code can effortlessly port to VyperCore’s platform and start to measure the accelerated performance.

VyperCore, founded in 2022 to commercialise PhD research by Ed Nutting at the University of Bristol, has rapidly grown to a team of fifteen, with design centres in Bristol and Cambridge. After a $5 million funding round in March 2023, the company also joined the Silicon Catalyst accelerator program and is part of the UK Intel Ignite program.

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